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**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99
Chips:
[82443ZX] (PAC) [82371EB] (PIIX4E)
CPUs: Single P-II/Celeron
DRAM Types: EDO SDRAM
Mem Rows: 4
DRAM Density: 16Mbit 64Mbit
Max Mem: 256MB
ECC/Parity: No
AGP speed: 1x 2x
Bus Speed: 66 100 133*1
PCI Clock/Bus: 1/2 1/3 1/4*1 PCI 2.1
440ZX-66 is the same but only has bus speed of 66 MHz and PCI divisor
or 1/2.
>*1 Exists but unofficially. There is no 1/2 divider for AGP,
making AGP unstable in a 133MHz bus system. In this config. the
system is overclocked.
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470 'Mozart' 486/386 EISA chipset c:Dec91
***Info:
The SL82C470 chip set provides a very high performance. highly inte-
grated and cost-effective implementation for personal computer systems
based on the standard EISA bus. It supports both 386DX and 486DX/SX
CPUs over the entire performance range, from 20Mhz to 50Mhz. The chip
set can operate in either "conventional" or "concurrent" config-
uration. Under the conventional configuration, the cache subsystem is
dedicated to bus snooping when a DMA or master device becomes active.
Under the concurrent configuration, the CPU-cache operation continues
while bus snooping is performed for the DMA or master device to
explore maximum concurrency between the CPU and the EISA bus. Only
ten TTLs are required for a complete motherboard design under the
conventional configuration in addition to the chip set and memory
devices. Five additional TTLs are required for the concurrent
configuration. A complete EISA system of either configuration can be
easily implemented on a baby AT sized motherboard.
The SL82C470 chip set consists of three 160-pin PQFP devices: the
SL82C471 integrated cache/DRAM controller, the SL82C472 EISA bus
controller and the SL82C473 DMA controller.
SL820471 Cache/DRAM Controller
The SL82C47l Cache/DRAM controller controls the cache and DRAM
accesses from the CPU, EISA/ISA masters and DMA devices. The chip
adapts a write-back cache scheme to minimize the interference between
the CPU-cache and DMA/master during their concurrent operations. The
cache size ranges from 64KB to 1MB with advanced features such as
2-1-1-1 burst line fill. Snoop-filtering, local bus support and
programmable non-cacheable and write-protected regions. The page mode
DRAM controller supports 1 to 4 banks of DRAMS up to 256MB. A mixture
of 256KB, 1MB. 4MB and 16MB DRAMs is supported. The video and system
BIOS can be shadowed or cached independently. The cache-DRAM
subsystem allows zero wait state burst mode DMA transfers to take full
advantage of the high bandwidth of the EISA bus.
The DRAM data bus can either be connected directly to the CPU local
bus or be buffered externally, The control signals for the external
buffers are generated by the SL82C471.
SL82C472 EISA Bus Controller
The SL82C472 EISA bus controller translates bus control signals
between the CPU, EISA/ISA and DMA masters and slaves. The chip also
includes buffers and byte/word swap logic between the CPU (or DRAM)
and the EISA bus. The bus conversion and data alignment are performed
automatically.
The SL82C472 includes two 8259 interrupt controllers and four 8254
timer channels modified for 100% EISA compatibility. The chip also
includes parity generation and check logic and NMI and timeout logic.
SL82C473 EISA DMA Controller
The SL82C473 DMA controller implements seven EISA DMA channels. the
system arbiter and the co-processor interface logic. The DMA control-
ler supports compatible type A, type B and type C (burst) mode
operations with the buffer chaining capability. The multilevel
rotating priority arbitration with fail-safe timeout is implemented
for the system arbiter. Six sets of slot-specific master handshake
signals (MACK and MREQ) are provided directly without any external
components.
The address latches and buffers for the EISA bus are also included in
the SL82C473.
***Configurations:...
***Features:...
**SL82C490 'Wagner' 486? [no datasheet] ?...
**SL82C550 'Rossini' Pentium [no datasheet] c:95...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9025 Address Controller <Jan90
***Info:...
***Versions:...
***Features:...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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