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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9025 Address Controller <Jan90
***Info:
The SL9025 Address Controller is a member of VIA's FlexSet family that
efficiently integrates the PC/ AT system logic.
The SL9025 is part of the Core AT Logic chips that implement the
system logic common to 80286, 80386SX, 80386DX and 80486-based PC / AT
designs. It supports up to 25 MHz performance. In addition to the
SL9025, the Core AT Logic chips consists of the SL9011 System
Controller, the SL9020 Data Controller, the SL9030 Integrated
Peripheral Controller and the 9X5X Memory Controller.
It is designed using advanced 1.5 micron, double layer metal CMOS
process and is offered in a 100 pin plastic flatpack package.
SL9025 is a general purpose address controller for PC/ AT. It can be
used with 16 or 32 bit CPUs including 80286, 80386SX, 80386DX or
80486. The device includes all necessary latches, buffers, and drivers
for CPU Address Bus (A-Bus), System Address Bus (SA-Bus), and
Peripheral Address Bus (XA-Bus). In addition, Port-B, NMI, Parity
Latch and I/O Decode Logic as well as Refresh for 256K, IM or 4M DRAMs
is provided. Optional XD to XA transfer latches are also provided.
High drive buffers (12mA-24mA) are provided for full PC / AT
compatibility.
***Versions:...
***Features:...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
*VLSI...
*Western Digital...
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*ZyMOS...
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