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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C700 FireStar c:97
***Info:...
***Configurations:...
***Features:
PCI Bus
o PCI supports sustained X-1-1-1 bursts, even to DRAM through an
innovative mechanism. PCI operation can be concurrent with
CPU/L2 cache and IDE operations.
o PCI clock generation eliminates the need for external PCI clock
buffers in many designs and allows the PCI bus to be effectively
power-managed.
o 3.3V or 5.0V PCI is supported on the FireStar PCI bus. If FireStar
is configured for 3.3V operation, 5.0V-only PCI plug-in cards and
docking stations can still be supported through a bridge device
such as OPTi's 820824 Cardbus Controller/Docking Solution, whose
prefetch and post-write buffers off-load operations from the
primary PCI bus.
DRAM Controller
o Provides BIOS with the means to automatically detect the DRAM type
in use on each bank, whether fast page mode, EDO, or synchronous
DRAM, allowing BIOS routines to efficiently program DRAM
operation.
ISA Bus
o A full ISA bus is directly provided to support the keyboard
controller, BIOS ROM, and Compact ISA peripheral devices for local
ISA support with no TTL. When reduced ISA operation is selected,
other FireStar pins become available for general purpose use.
Bus Mastering IDE
o FireStar supports two bus mastering IDE channels that function
concurrently with operations on the CPU/L2 cache interface and PCI
interface. Up to four drives are supported.
o An emulated bus mastering IDE feature allows IDE drives that are
not commonly available as bus mastering devices, such as CD-ROM
drives, to act as bus mastering drives. For example, a CD-ROM
drive can transfer video data to DRAM while the CPU is
decompressing the data and sending it to the graphics controller.
Thermal Management
o Fail-safe thermal management incorporates feedback logic that
requires a very inexpensive external sensor circuit.
o Hardware monitors temperature directly and reliably, while the
fail-safe aspect of the circuitry ensures that sensor component
failure will automatically inhibit CPU clocking to prevent
overheating.
o SMM code will be able to read (and display if desired) actual CPU
temperature.
ACPI Implementation
o Microsoft Advanced Configuration and Power Interface (ACPI) is
being implemented in the FireStar silicon. ACPI is a standard
register interface for power management function jointly developed
by Microsoft, Intel, and Toshiba.
Miscellaneous
o The standard version of the chip can run at 3.3V, up to 66MHz on
the CPU bus.
o A new Context Save Mode feature allows chip registers to be saved
and restored more efficiently than ever before, requiring less SMM
code and storage space.
o The OPTi Viper-N+ Power Management Unit is used, maintaining
backward compatibility down to the register level with previously
written support firmware.
o Serial IRQs are supported as an option for interrupts on PCI.
o Known devices in the system can be positively decoded on the PCI
bus, eliminating the delay for subtractive decode and improving
the efficiency of ISA operations.
o ISA bus cycle speed can be individually controlled to certain ISA
device groups.
o Simple logic gate functions can be assigned to unused pins to
eliminate the need for external TTL. Pin programming is far more
flexible than ever possible on any other chip.
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**SL9020 Data Controller <Jan90
***Info:
The SL9020 Data Controller is a member of VIA's FlexSet family that
efficiently integrates the PC / AT system logic.
The SL9020 is part of the Core AT Logic chips that implement the
system logic which is common to all microprocessors such as 80286,
80386SX, 80386DX and 80486-based PC / AT designs and supports up to 25
MHz performance. In addition to the SL9020, the Core AT Logic chips
consists of the SL9011 System Controller, the SL9025 Address
Controller, the SL9030 Integrated Peripheral Controller and the SL9X5X
Memory Controller.
It is designed using advanced 1.5 micron, double layer metal CMOS
process and is offered in a 100 pin plastic flatpack package.
The SL9020 provides the data buffer latches and drivers for a 16-bit
data path for PC/ AT using 80286 and 80386SX type processor. Two
SL9020 can be used to construct a 32-bit data path for PC/ AT's using
an 80386DX microprocessor.
Control logic and drivers for the chip includes CPU Data Bus (D Bus),
Memory Data Bus (MD Bus), System Data Bus (SD Bus) and Peripheral Data
Bus (XD Bus). The SL9020 also performs parity generation/ checking,
low to high byte transfer on SD Bus and drivers for low and high byte
Column Address Strobes (CAS) for two independent memory banks. Latched
CPU Byte enable (BHE0 & BHE1) are also provided.
All Data bus outputs are capable of high drive (12-24mA) and have fast
rise & fall times of 5ns.
Latches are also provided on D to MD, MD to D, and SD to D paths.
***Versions:...
***Features:...
**SL9025 Address Controller <Jan90...
**SL9030 Integrated Peripheral Controller <Jan90...
**SL9090/A Universal PC/AT Clock Chip <oct88...
**SL9095 Power Management Unit ?...
**SL9151 80286 Page Interleave Memory Controller (16-25MHz) ?...
**SL9250 80386SX Page Mode Memory Controller (16/20MHz 8MB) ?...
**SL9251 80386SX Page Interleave Memory Controller <04/13/90...
**SL9252 80386SX System and Memory Controller <06/12/90...
**SL9350 80386DX Page Mode Memory Controller (16-25MHz 16MB) ?...
**SL9351 80386DX Page Interleave Memory Controller (33MHz) ?...
**SL9352 80386DX System and Memory Controller <06/12/90...
**SLXXXX Other chips...
**
**VT82C470 "Jupiter", Chip Set (w/o cache) 386 [no datasheet] ?
**VT82C475 "Jupiter", Chip Set (w/cache) 386 [no datasheet] ?
**VT82C486/2/3 "GMC chipset" [no datasheet, some info] ?...
**VT82C495/480 "Venus" Chip Set [no datasheet] ?
**VT82C495/491 ? EISA Chip Set [no datasheet, some info] <93...
**VT82C496G Pluto, Green PC 80486 PCI/VL/ISA System <05/30/94...
**VT82C530MV 3.3V Pentium chipset [no datasheet, some info]<05/30/94...
**VT82C570M Apollo Master, Green Pentium/P54C <06/22/95...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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*Western Digital...
*Winbond...
*ZyMOS...
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