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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*SIS...
**85C496/497     486-VIP 486 Green PC VESA/ISA/PCI Chipset         <95
***Info:...
***Configurations:...
***Features:
o   Host Bus
    - Supports Intel 486, P24D, P24T, DX4, SL
    - Enhanced 486, AMD 486, Enhanced Am486, and Cyrix M7/Cx 5x86
      in 25/33/40/50 Mhz, 5V CPU.
o   VESA Bus Slave
    - Supports VESA Bus Specification Rev. 2.0p with Local Device 
      Target only.
o   PCI Local Bus
    - Supports PCI Bus Specification Rev. 2.0 with up to 4 PCI Masters
    - Implements 3 Level Post Write Buffer for CPU write PCI Target 
      Memory Cycle.
    - Supports Back to Back Single Memory Write to PCI Burst Write.
    - Supports PCI Interrupt Steering with Four PIRQ Inputs.
    - Supports PCI Master Burst Accesses On-Board Memory Up to 64 
      Double Word Long.
    - Supports Concurrency PCI Bus.
    - Snoop  Filter  and  Advanced  Snooping  for  Reducing CPU Snoops 
      During Sequential PCI Master Accesses On-Board Memory Cycles.
    - Supports PCI Bus PCI to PCI Bridge.
o   Supports L1 Cache Write Back CPU (P24T/P24D/M7/Enhanced Am486) 
    systems
o   Supports Cx 5x86 Linear Burst Order Mode.
o   L2 Cache Controller
    - Write-Back or Write-Through Schemes
    - Bank Interleave/Non-Interleave Cache Access
    - Cache Size: 64K/128K/256K/512K/1MB
    - 8 bit or 7 bit Tag (Combined Tag and Dirty SRAM) with  
      Direct-Mapped cache organization.
    - Optional Separate Dirty SRAM.
o   DRAM Controller
    - Supports 8 Banks Non-Interleaved Access for Single and Double 
      Sided SIMMs up to 255 MBytes.
    - Supports DRAM CAS Before RAS Refresh.
    - Supports "Table-Free" DRAM configuration.
    - Programmable driving current for the DRAM signals.
    - Supports Symmetrical and Asymmetrical DRAMs.
    - Supports 256K/512K/1M/2M/4M/8M/16M/32M xN Fast Page Mode and 
      EDO DRAM.
o   Built-In Local Bus IDE Interface
    - Supports Data Conversion for the Double Word Accessing
    - Supports Symmetry Configuration for Channel 1 and Channel  
      0,  PIO  Mode  IDE  Hard Disks.
    - Supports Mode 3 and above Timing.
    - Supports Individual Drive Timing Setting for Optimal Performance
    - Supports Posted Write Buffers and Pre-fetch Buffer.
    - Supports Primary IDE or Secondary IDE Addressing (1Fx/17x)
o   Fast-Slow Link Interface
    - Linkage to ISA Bridge by FS-Link Interface.
    - Fast Access to BIOS, ISA Memory Holes, and Interrupt Acknowledge 
      Cycle by FS-Link.
    - Two Programmable Non-Cacheable Regions 
    - Two Programmable PCI Memory Holes and One Programmable ISA 
      Memory Holes.
o   208-Pin PQFP
o   0.6um Low Power CMOS Technology

**85C501/502/503 Pentium/P54C PCI/ISA Chipset                <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
**S
***Shasta...
***SARC...
***ServerWorks (Reliance Computer Corporation)

From: http://www.quepublishing.com/articles/article.aspx?p=481869&seqNum=7

"Starting in 1997, ServerWorks (a Broadcom company originally known as
Reliance Computer  Corporation) introduced  its first  server chipsets
for Intel  processors. Today, ServerWorks  is second only to  Intel as
the major supplier of server chipsets for Intel-based servers.

Early ServerWorks chipsets included the ServerSet I (also known as the
Champion 1.0 chipset)  and the ServerSet II. ServerSet  I supported up
to  six   Pentium  Pro   processors  and   featured  two   32-bit  PCI
buses. ServerSet  II supported up  to four Pentium II  Xeon processors
and  featured  a 64-bit  PCI  bus.  These chipsets  were  discontinued
several years ago."

Others:
****Serverset III LE ...
****Serverset III HE [NB6536] ...
****Serverset III WS ...
****Serverset III HESL ...
***Sun Electronics (SUNTAC) ...
***Syslogic...
***Other...
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*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...