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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:
The  HT44 is  a  look-aside write-through,  80486SX,  486DX or  486DX2
secondary cache  controller. It is  packaged in an  inexpensive 84-pin
plastic-leaded chip carrier (PLCC).

Architecture
With  its look-aside architecture,  the HT44  fits beside  the CPU-to-
Memory bus  and not in  the data path.   Therefore, once the  HT44 has
been designed  into a  486 system, it  can be populated  for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.

Performance
The  HT44  has a  number  of  performance  enhancing features.   These
include zero-waitstate burst line fills  to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.

Memory Configurations
The HT44 supports  cache sizes from 32KBytes to  1MB. Both synchronous
and asynchronous  SRAMs are supported.  25ns SRAMs are  sufficient for
zero-wait-state operation at 33MHz.

Chip Set Support
The HT44 can,  be implemented with minimal glue logic  in a 486 system
with the  HTK340 (code  name Shasta) chip  set.  The registers  in the
HTK340  allow  for programming  of  non-cacheable and  write-protected
areas of  memory. The  HTK340 will support  the HT44  with synchronous
SRAMs only.   Future Headland chip sets will  support both synchronous
and asynchronous SRAM designs.

The HT44  can also be used  with some third-party  chip sets, however,
additional glue logic may be required.

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**Other chips:
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***Peripheral:...
***Other:
UM3750A         Programmable 12-bit Encoder/Decoder
UM6502/07/12    8-bit Microprocessor 1,2,3,4 MHz Versions
UM6502E         8-bit Microprocessor 1,2,3,4 MHz Versions
UM8048/35/49/39 Microcontroller
UM8051/31       Microcontroller
UM74HCT590      8 bit Binary Counter with Output Registers
UM74HCT646      Octal Bus Transceiver and Register

UM2332/UM2333/UM2364  Mask ROM 
UM2366/A              Mask ROM
UM23128/A             Mask ROM
UM23256/A             Mask ROM
UM2147/UM2148/UM2149  SRAM
UM6104/UM6104-1       SRAM
UM6114/UM6116-2/-3/-4 SRAM
UM6116-5/UM6164       SRAM
UM6167/UM6168         SRAM

UM9001/UM9003AF Network?
UM9007F/UM9008  Network?
UM9009          Network?
UM9017F/UM9018  Ethernet
UM9026          Fast Ethernet
UM9090          Network?


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