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**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95
***Notes:
According to:
https://www.thefreelibrary.com/ALi+Announces+Latest+Aladdin+Family+Entry+New+Core+Logic+Chip+Set+for...-a016766656

" SAN JOSE,  Calif.--(BUSINESS WIRE)--April 4, 1995--Acer Laboratories
Inc. (ALi) today introduced its newest Aladdin core logic chip set for
Pentium-class personal computers.

This  chip set  -  the M1511/M1513/M1512  - provides  high-performance
along with the highest  level of integrated functions, allowing design
of significantly cost-reduced, high-performance system boards. The new
Aladdin chip set  supports the Intel Pentium family up  to 150 MHz, as
well as all future higher speed  Pentium versions; the AMD K5; and the
Cyrix M1 including linear mode addressing support.

This new chip  set in ALi's Aladdin Family  includes the M1511 Memory,
Cache, Buffer controller, the M1513  SIO Controller and two M1512 data
buffers. The chip set  provides cache flexibility supporting Pipelined
Burst, Burst and Standard SRAMs; up to 1MB cache. High performance EDO
DRAM or DRAM  can be used up  to 768MB in six banks.  Bus Mastered IDE
and a Keyboard Controller are  integrated, reducing parts count on the
system board. APIC is also integrated to allow for dual-Pentium system
design,  and  plug  &   play  features  are  included  for  multimedia
platforms.

"The Aladdin chip  set family is targeted at  the mainstream PC market
which is driven by high performance and cost," said Dr. S. J. Lee, ALi
Vice President of Technology. "This second generation Aladdin provides
the  additional  integrated functions  and  higher performance  levels
which together help system  manufacturers meet the performance and the
required  cost  levels  to  compete  profitably  in  the  increasingly
competitive Pentium system market."

Pricing and Availability

All devices are  manufactured in a 0.6-micron CMOS  process. The M1511
and 1513 are packaged in 208-pin  PQFPs and the M1512s are packaged in
100-pin PQFPs. The chip set will be sampling in April and is priced at
$22.00 in volume quantities. 
"

***Configurations:...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
**
**Support Chips:
**M1535/D        South Bridge                                        ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
*UMC...
**UM82c45x     Serial/Parallel chips                                 ?
***Notes:...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...