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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**TACT82000   3-Chip 286 [no datasheet]                            c89
***Notes:...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
*UMC...
**UM82C206     Integrated Peripheral Controller                    <91
***Info:...
***Versions:...
***Features:
o   Fully compatible with PC/AT architecture
o   Fully compatible with 8237 DMA controller, 8259 Interrupt 
    controller, 8254 Timer/Counter, and 146818 Real Time Clock
o   Provides 7 DMA channels, 13 Interrupt request channels, 2 Timer/
    Counter channels, and a Real Time Clock
o   Built in 74LS612 memory mapper for DMA page address
o   Provides 114 bytes of CMOS RAM memory
o   8 MHz DMA clock with programmable internal divider for 4 MHz 
    operation
o   16M bytes DMA address space
o   Programmable wait states for the DMA cycle
o   Reduced recovery time (120 ns) between I/O operations 



**UM82c45x     Serial/Parallel chips                                 ?...
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