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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
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*UMC...
**UM82C206     Integrated Peripheral Controller                    <91
***Info:
The UM82C206  Integrated Peripheral  controller includes two  8237 DMA
controllers, two  8259 Interrupt controllers, one  8254 Timer/Counter,
one MC146818 compatible  Real Time Clock, an additional  64 bytes CMOS
RAM,  one  74LS612   memory  mapper,  and  some   top  level  decoder/
configuration logic circuits.  It is a single chip  integration of all
main peripheral  parts attached  to the X  bus of  PC/AT architecture.
While  providing  full  compatibility  with  PC/AT  architecture,  the
UM82C206  also  offers  some  enhanced  features  and  improved  speed
performance. These  include an additional  64 bytes of  user definable
CMOS RAM in real time clock  and drastically reduced recovery time for
the 8237, 8259  and 8254.  Programmable wait state  option is provided
for the DME  cycles and CPU I/O cycles accessing  this chip. This chip
also  provides programmable  8  or  4 MHz  DMA  clock selection.   The
UM82C206 is implemented using advanced 1.5u CMOS design technology and
is packaged in an 84-pin PLCC.

***Versions:...
***Features:...
**UM82c45x     Serial/Parallel chips                                 ?...
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