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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:
o   Two-Way, Set Associative, Secondary Cache for i860 XP 
    Microprocessor
o   50 MHz "No Glue" Interface with CPU
o   Configurable
    - Cache Size 256 or 512 Kbytes
    - Line Width 32, 64 or 128 Bytes
    - Memory Bus Width 64 or 128 Bits
o   Dual-Ported Structure Permits Simultaneous Operations on CPU and
    Memory Buses
o   Efficient MRU Way Prediction
    - Zero Wait States on MRU Hit
    - One Walt State on MRU Miss
o   Dynamically Selectable Update Policies
    - Write-Through
    - Write-Once
    - Write-Back
o   MESI Cache Consistency Protocol
o   Hardware Cache Snooping
o   Maintains Consistency with Primary Cache via Inclusion Principle
o   Flexible User-Implemented Memory Interface Enables Wide Range of
    Product Differentiation
    - Clocked or Strobed
    - Synchronous or Asynchronous
    - Plpelining
    - Memory Bus Protocol
o   82495XP Cache Controller Available in 208-Lead Ceramic Pin Grid 
    Array Package
o   82490XP Cache RAM Available in 84-Lead Plastic Quad Flatpack 
    Package

**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*UMC...
**UM82C206     Integrated Peripheral Controller                    <91
***Info:
The UM82C206  Integrated Peripheral  controller includes two  8237 DMA
controllers, two  8259 Interrupt controllers, one  8254 Timer/Counter,
one MC146818 compatible  Real Time Clock, an additional  64 bytes CMOS
RAM,  one  74LS612   memory  mapper,  and  some   top  level  decoder/
configuration logic circuits.  It is a single chip  integration of all
main peripheral  parts attached  to the X  bus of  PC/AT architecture.
While  providing  full  compatibility  with  PC/AT  architecture,  the
UM82C206  also  offers  some  enhanced  features  and  improved  speed
performance. These  include an additional  64 bytes of  user definable
CMOS RAM in real time clock  and drastically reduced recovery time for
the 8237, 8259  and 8254.  Programmable wait state  option is provided
for the DME  cycles and CPU I/O cycles accessing  this chip. This chip
also  provides programmable  8  or  4 MHz  DMA  clock selection.   The
UM82C206 is implemented using advanced 1.5u CMOS design technology and
is packaged in an 84-pin PLCC.

***Versions:...
***Features:...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
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