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**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
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**SL82C550 'Rossini' Pentium [no datasheet] c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
The Symphony "Rossini" Chipset (Symphony Labs: 10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates with up to 66 MHz external clock rates, up to two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache, EDO RAM, and does dual-port busmastering IDE. It will,
apparently, adjust the voltages to its various (CPU, PCI, cache, RAM)
buses to suit their requirements, and will control up to six PCI
masters. It consists of the SL82C551 cache/memory controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
**UM82C852 Multi I/O For XT <91
***Info:...
***Versions:...
***Features:
o Supports game port
o Supports 2nd serial port
o Centronics printer interface
o Independent control of transmit, receive, line status and data set
interrupts
o Individual modem control signals
o Programmable serial interface characteristics:
— 5, 6, 7 , or 8 bit characters
— Even, odd or no-parity bit generation and detection
— 1, 1-1/2, or 2 stop bit generation
o Milliseconds through month counters for real time clock 56 bits of
RAM
with comparator for comparing the real time counter to the RAM
data
o POWER DOWN input that disables all inputs and outputs
o Disables the chip from the reset of the system for standby low
power operation by use of a POWER DOWN input
o 32,768 Hz crystal for real time clock
o Four-year calendar (no leap year)
o 24-hour clock
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
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