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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**HT44          Secondary Cache                                c:Jun92
***Info:...
***Versions:...
***Features:
General Features
o   Support for 4868X/DX/DX2 CPUs
o   System implementation with Headland’s HTK340 chip set and future 
    486 chip sets
o   16, 20, 25 and 33 MHz CPU speeds

Memory Configurations
o   32KB, 64KB, 128KB, 256KB, 512KB & 1MB cache sizes
o   25ns SRAMs required at 33 MHz
o   Asynchronous and synchronous SRAMs are supported
o   Programmable write-protected and non-cacheable regions are 
    supported through the chip set

Architecture
o   Look-Aside
o   Write through
o   Direct mapped
o   Integrated tag comparator
o   Zero wait state cache hits
o   Simultaneous 486 and secondary cache update on read miss
o   486 line burst cycle support
Package & Die
o   84-pin PLCC
o   LSI Logic’s 0.7 micron HCMOS process

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**UM82C852     Multi I/O For XT                                    <91
***Info:
The  Multi-I/O  chip, UM82C852  is  an  integrated  chip of  UM82C450,
UM82C11, UM82C8167. This  chip is a Multi-I/O for  PC/XT and PS2 model
30.

The   82C450  asynchronous   communications  element   (ACE)  performs
serial-to-parallel  conversion   on  data  characters   received  from
peripheral  devices or  modems, and  parallel-to-serial  conversion of
data characters transmitted by the CPU. The complete status of the ACE
can  be read  at  any time  during  functional operation  by CPU.  The
information obtained  includes the type and condition  of the transfer
operations being performed and error conditions.

The  82C11  parallel  port  provides  the user  with  a  bidirectional
parallel data  port that fully  supports the parallel  Centronics type
printer.

The 82C8167 real time clock includes an addressable real time counter,
56 bits  of static RAM with  an on chip oscillation  circuit which can
generate the 32,768 Hz time base.

The 82C852 is packaged in a 68-pin plastic leaded chip carrier.
***Versions:...
***Features:...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
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