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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



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*UMC...
**UM82C480     386/486 PC Chip Set                                 c91
***Info:...
***Configurations:...
***Features:
o   100% IBM PC/AT compatible
o   Supports 80386 CPU running at 25/33/40 MHz
o   Supports 80486 CPU running at 25/33/40/50 MHz in 1x clock
o   Supports Intel 80387 / Weitek 3167 / Weitek 4167 Floating Point 
    Coprocessors
o   Built-in cache controller:
    - Direct-mapped organization with write-back operation
    - 0 wait state for cache hit
    - Flexible cache size: 32/64/128/256/512/1024 KB
    - Hidden DRAM refresh to boost system performance
    - built-in registers to support three independent non-cacheable 
      regions
    - Support cache line fill as well as 80486 burst mode
    - Support Automatic Memory Size Detection
o   Sophisticated DRAM controller:
    - Supports Fast/Standard page mode
    - Supports 4 banks CPU speed DRAM with memory size up to 64MB
    - Supports mixable 256Kx9, 1Mx9, 4Mx9 DRAM modules
    - Programmable DRAM wait states
    - Supports 256KB or 384KB (A to F segments of first 1MB) 
      relocation to the top of DRAM memory
o   Supports sophisticated Shadow RAM for video and system BIOS (C, D,
    E, F segments)
o   Supports first GATE A20 and fasy CPU RESET to optimize OS/2 
    operations
o   Synchronous AT bus clock with programmable clock (divided by 2, 3,
    4, 5, 6)
o   Programmable CPU clock (divided by 1, 2, 3, 4)
o   Support 256KB/512KB/1MB EPROMs with single or double EPROM BIOS 
    configuration

**UM82C493/491 ??????????????? [no datasheet]                        ?...
**UM8498/8496  486 VL Chipset  "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886  HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890       Pentium chipset [no datasheet]                        ?...
**
**Support Chips:
**UM82152      Cache Controller (AUStek A38152 clone)              <91...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
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*ZyMOS...
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