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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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*UMC...
**UM82C088 PC/XT Integration Chip <91
***Info:...
***Configurations:...
***Features:
o Fully IBM-PC/XT compatible
o 82C84 Clock generator with 2 clock-inputs to generate the CPU
clock. These are 14.318 MHz and 30 MHz which will support 4.77 MHz
and 10 MHz CPU clocks with 1/3 duty cycle.
o 82C88 Bus Controller
o 82C37 4 channel DMA controller, channel is used for DRAM refresh
o 82C59 8 channel interrupt controller, level is used for system
time base, and level 1 for keyboard input
o 82C53 3 channel timer, channel is used for system time base,
channel 1 for DRAM refresh, and channel 2 for speaker audio
o 82C55 Peripheral l/O r used for keyboard interface and system
configuration switch (same as the PC/XT)
o 74322 Keyboard interface, supports PC/XT type keyboard
o 74280 Parity check and generator
o 74670 4 bit page register for DMA
o Wait state logic
o NMI control logic
o ROM decoder for one 2764 and one 27256
o RAM decoder for 4164 or 41256 DRAM
o H/W and S/W CPU speed change and indicator
o Built-in delay line for RAS, CAS
o Low power consumption: less than 300 mW at 10 MHz CPU speed
o Small PCB size: 100 pin plastic Flat package
**UM82C230 286AT MORTAR Chip Set <91...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
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*Winbond...
*ZyMOS...
*General Sources:...
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