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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
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**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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**TACT83000 AT 'Tiger' Chip Set (386) c89
***Info:
The Texas Instruments TACT83000 AT Chip Set is designed for cached and
noncached 386-based PC-AT compatible systems running at speeds up to
33 MHz. Manufactured with high-speed 1-um CMOS EPIC technology, the
chip set is functionally partitioned into three devices: the TACT83443
AT Bus Interface Unit (ATU), the TACT83442 Memory Control Unit (MCU),
and the TACT83441 Data Path Unit (DPU). The ATU is packaged in a
208-lead plastic quad flatpack (QFP), while the MCU and DPU are
packaged in 100-lead plastic QFPs
These three chips, along with four other logic chips, comprise all the
logic necessary for a fully compatible 16-bit 3868X-based system.
Since one DPU provides a 16-bit data path, a 32-bit 386DX-based system
requires an additional DPU.
With software-controlled configuration registers on board the ATU and
MCU, the chip set supports a wide variety of PC system config-
urations. For complete programming details, see the TACT8300 AT Chip
Set User’s Guide, literature number SRZU001.
***Configurations:...
***Features:...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
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