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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89
***Info:...
***Configurations:...
***Features:
o   High-Speed 1-um CMOS Technology Supports System Speeds up to 
    33 MHz
o   Fully AT-Compatible 386 Three-Chip SX, Four-Chip DX Solutions
o   Only Four Additional Logic Chips Needed
o   Major Features Programmable Through Software
o   TACT83442 Memory Control Unit (MCU)
    - Cascadable up to Eight Devices
    - Address Range of up to 32M Byte Per Device, 256M Byte Fully 
      Cascaded
    - Supports 256K-, 1M-, and 4M-Bit DRAMs in Normal, Page, Word-
      interleave, and Page Block-interleave Modes
    - Programmable DRAM Timing Parameters
    - Supports up to Two Memory Banks for 32-Bit Systems and Four 
      Banks for 16-Bit Systems
    - Can Directly Drive up to 36 DRAM Devices
    - Shadow RAM Available Between 0C 0000h and 0F FFFFh
    - Contains Global Page Mapping RAM Allowing Remap of 
      - 64K-Byte Memory Blocks Above 1M Byte
      - 16K-Byte Memory Blocks Below 1M Byte
o   TACT83443 AT Bus Interface Unit (ATU)
    - Internal Clock Switching Between Two Independent Frequencies 
      Controlled by Software
    - Asynchronous AT Bus Interface With Write Buffer Option
    - Full AT Direct-Drive Capability
    - Extended Direct Memory Access Mode for 32-Bit Operation
    - Fast CPU Reset and A20 GATE Modification
    - Numeric Processor Interface for 387SX, 387DX, and Weitek 3167
    - Integrates All Essential AT Peripherals
    - Real Time Clock With 128-Byte CMOS RAM
o   TACT83441 Data Path Unit (DPU)
    - 8- and 16-Bit Data Bus Sizing
    - Data Path Cascadable to 32 Bits
    - Write Buffer Capability for AT Bus Access
    - Supports Posted Write Operations From Cache Controller
    - Parity Generation and Checking Logic

**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
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