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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
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*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:
The HT44 is a look-aside write-through, 80486SX, 486DX or 486DX2
secondary cache controller. It is packaged in an inexpensive 84-pin
plastic-leaded chip carrier (PLCC).
Architecture
With its look-aside architecture, the HT44 fits beside the CPU-to-
Memory bus and not in the data path. Therefore, once the HT44 has
been designed into a 486 system, it can be populated for secondary
cache systems or left vacant for non-secondary cache systems. The HT44
is direct-mapped to the available address space.
Performance
The HT44 has a number of performance enhancing features. These
include zero-waitstate burst line fills to the 486 on secondary cache
hits, and simultaneous 486 and secondary cache updates on read misses.
Memory Configurations
The HT44 supports cache sizes from 32KBytes to 1MB. Both synchronous
and asynchronous SRAMs are supported. 25ns SRAMs are sufficient for
zero-wait-state operation at 33MHz.
Chip Set Support
The HT44 can, be implemented with minimal glue logic in a 486 system
with the HTK340 (code name Shasta) chip set. The registers in the
HTK340 allow for programming of non-cacheable and write-protected
areas of memory. The HTK340 will support the HT44 with synchronous
SRAMs only. Future Headland chip sets will support both synchronous
and asynchronous SRAM designs.
The HT44 can also be used with some third-party chip sets, however,
additional glue logic may be required.
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*TI (Texas Instruments)...
**TACT82411 Snake Single-Chip AT Controller c90
***Notes:...
***Info:
The new Texas Instruments single chip TACT82411 contains the system
logic and most of the peripheral functions needed to build a 12-20 MHz
80286-based computer that is 100% compatible with the IBM PC-AT. Only
seven logic components plus memory, CPU, and coprocessor are required
to complete an 80286 system board. The chip also supports system
boards which use the 80386SX. The TACT82411 is packaged in a 208-pin
quad flat pack (QFP).
Because the TACT82411 is manufactured with TI's 1-micron EPIC CMOS
technology, it provides a high level of integration and high-speed
state-of-the-art performance at relatively low power consumption. This
combination permits systems that are smaller, lighter, and more
sophisticated, but with lower power consumption - an ideal comab-
ination for portable, battery-powered systems such as laptop com-
puters. Another benefit of high-integration is increased reliability
due to fewer board connections. In addition, product cost is reduced
because new system design and testing are simplified.
Redesign of existing multi-chip or discrete 80286 system boards is
easy and cost-effective because of the straightforward and flexible
structure of the TACT82411 chip. System boards which were originally
designed to operate at 12/16 MHz can be easily upgraded to operate at
20 MHz. Non-PC applications using the 80286, such as instrument con-
trol, automobiles, and medical equipment, can also benefit by using
the TACT82411 chip. Architectural variations can be easily implemented
for special-purpose systems such as LAN-based diskless workstations
and PC-based portable test equipment.
***Configurations:...
***Features:...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
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