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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers          <84
***Notes:...
***Info:
Each 'LS610  and 'LS612  memory mapper  integrated circuit  contains a
4-line to  16-line decoder, a  16-word by  12-bit RAM, 16  channels of
2-line to 1-line multiplexers, and  other miscellaneous circuitry on a
monolithic chip. Each  'LS610 also contains 12 latches  with an enable
control.

The memory  mappers are designed  to expand a  microprocessor's memory
addressing capability by  eight bits. Four bits of  the memory address
bus (see  System Block Diagram)[see  datasheet] can be used  to select
one of 16 map registers that contain  12 bits each.  these 12 bits are
presented  to the  system memory  address bus  through the  map output
buffers  along with  the  unused  memory address  bits  from the  CPU.
However, addressable memory space  without reloading the map registers
is the  same as would  be available with  the memory mapper  left out.
The  addressable  memory  space  is  increased  only  by  periodically
reloading the  map registers  from the  data bus.   This configuration
lends itself  to memory utilization  of 16 pages of  2^(n-4) registers
each  without reloading  (n -  number of  address bits  available from
CPU).

These  devices have  four modes  of operation:  read, write,  map, and
pass.  Data may be read from  or loaded into the map register selected
by  the register select  inputs (RS0  thru RS3)  under control  of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map  operation will output the contents of the map
register selected by the map address  inputs (MA0 thru MA3) when CS is
high and  MM (map mode control)  is low. The 'LS612  output stages are
transparent in this mode, while  the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with  low levels in the other bit  positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000   3-Chip 286 [no datasheet]                            c89...
**TACT82411   Snake  Single-Chip AT Controller                     c90...
**TACT82S411  Snake+ Single-Chip AT Controller [no datasheet]      c91...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
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*Unresearched:...
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*ZyMOS...
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