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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:
The  82C802G/GP  provides  a  highly  integrated  solution  for  fully
compatible,  high  performance  PC/AT  platforms.  This  chipset  will
support  486SX/DX/DX2/DX4 and  P24T microprocessors  in the  most cost
effective  and power  efficient  designs available  today.  For  power
users this  chipset offers optimum performance for  systems running up
to 50MHz.

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C802G/GP  adds additional  memory configurations
and  extensive power management  control for  the processor  and other
motherboard components.

The  82C802G/GP supports  the latest  in write-back  processor designs
from Intel, AMD, and Cyrix, as  well as supporting the AT bus and VESA
local  bus for  compatibility and  performance.  It  also  includes an
82C206  Integrated  Peripherals  Controller  (IPC), all  in  a  single
208-pin PQFP (Plastic Quad Plat Pack) package for low cost.

Power Management Block
Figure  2-1  [see  datasheet]   exemplifies  the  flexibility  of  the
82C802G/GP/82C602   GREEN   strategy.   System  designs   can   easily
accommodate  both SLe and  non-SLe CPUs.  If an  Intel non-SLe  CPU is
used. SMI#, SMIACT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

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