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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:...
***Configurations:...
***Features:...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:...
***Versions:...
***Features:
o   Integrated direct mapped cache controller
o   Supports 486/386DX/386SX CPU
o   Supports both 1X and 2X CPU clock
o   Supports 486DX/SX/DX2/SLC up to 50 MHz
o   Supports 386DX/SX/SXLV up to 40 MHz
o   16KB to 4MB cache size
o   Line size from 1 to 4 doublewords
o   VL-Bus Master Device support
o   2-1-1-1 burst mode cache fill
o   Data streaming in external and internal cache
o   SRAM banks interleaving capability
o   Built-in tag comparator
o   Posted write buffer control
o   Cache invalidation support
o   Non-cacheable region support
o   387SX/387/3167/4167 interface
o   Arbitration between reset and HOLD
o   CMOS 100-pin RQFP package

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