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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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**SL82C365    Cache Controller (for 386DX/SX)                     c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from  16KB to  1MB  and line  size  ranged from  1  to 4  doublewords.
Without any  external logic, SL82C365 supports  1 to 4  banks of cache
SRAMs  independent of  the  line  size.  An  8-bit  tag comparator  is
integrated into the  chip which not only saves on  the system cost but
also improves  the overall performance.   25ns tag SRAM and  35ns data
SRAM   are  adequate   for   zero  wait   state  non-pipelined   33Mhz
operation. Assuming  8Kx8, 16Kx4, 32Kx8  and 64Kx4 SRAMs are  used for
tag SRAM, the selectable organization  is indicated in Table 1-1. [see
datasheet]  More options  are  available for  data RAM  configurations
because of the flexibility in  selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.

***Versions:...
***Features:...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
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