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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:
o   16 or 20 MHz Options.
o   Enhanced fast page mode design.
o   Programmable wait state options.
o   Shadow Ram feature.
o   Supports 8 M byte of on board memory.
o   Can use 256K x 1, 1 Meg x 1, and 256K x 4 DRAMs or a mix.
o   Supports 100 ns DRAMs at 16 MHz and 80 ns at 20 MHz.
o   Automatic remapping of 640K - 1 M RAM to top of the address space.
o   Advance CMOS Technology.
o   100 pin Flatpack.

**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
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**SL82C365    Cache Controller (for 386DX/SX)                     c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from  16KB to  1MB  and line  size  ranged from  1  to 4  doublewords.
Without any  external logic, SL82C365 supports  1 to 4  banks of cache
SRAMs  independent of  the  line  size.  An  8-bit  tag comparator  is
integrated into the  chip which not only saves on  the system cost but
also improves  the overall performance.   25ns tag SRAM and  35ns data
SRAM   are  adequate   for   zero  wait   state  non-pipelined   33Mhz
operation. Assuming  8Kx8, 16Kx4, 32Kx8  and 64Kx4 SRAMs are  used for
tag SRAM, the selectable organization  is indicated in Table 1-1. [see
datasheet]  More options  are  available for  data RAM  configurations
because of the flexibility in  selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.

***Versions:...
***Features:...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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