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**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C365    Cache Controller (for 386DX/SX)                     c:91
***Info:
The SL82C365 supports direct-mapped cache system with data size ranged
from  16KB to  1MB  and line  size  ranged from  1  to 4  doublewords.
Without any  external logic, SL82C365 supports  1 to 4  banks of cache
SRAMs  independent of  the  line  size.  An  8-bit  tag comparator  is
integrated into the  chip which not only saves on  the system cost but
also improves  the overall performance.   25ns tag SRAM and  35ns data
SRAM   are  adequate   for   zero  wait   state  non-pipelined   33Mhz
operation. Assuming  8Kx8, 16Kx4, 32Kx8  and 64Kx4 SRAMs are  used for
tag SRAM, the selectable organization  is indicated in Table 1-1. [see
datasheet]  More options  are  available for  data RAM  configurations
because of the flexibility in  selecting the number of banks. Refer to
section 1.13 [see datasheet] for detailed design examples.

***Versions:...
***Features:...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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