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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*HMC (Hulon Microelectronics)...
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**IBM AT: MC146818 Real Time Clock                                 <84
***Info:
The MC146818  Real-Time Clock  plus RAM is  a peripheral  device which
includes   the   unique   MOTEL   concept   for   use   with   various
microprocessors,  microcomputers,  and  larger computers.   This  part
combines  three unique  features:  a complete  time-of-day clock  with
alarm and one hundred year calender, a programmable periodic interrupt
and square-wave generator,  and 50 bytes of low-power  static RAM. The
MC146818  uses high-speed  CMOS  technology to  interface  with 1  MHz
processor busses, while consuming very little power.

The  Real-Time Clock  plus RAM  has two  distinct uses.  First,  it is
designed  as a  battery powered  CMOS part  (in an  otherwise NMOS/TTL
system) including  all the common battery backed-up  functions such as
RAM, time,  and calendar.  Secondly, the  MC146818 may be  used with a
CMOS  microprocessor  to  relieve  the  software  of  the  timekeeping
workload  and to  extend  the available  RAM  of an  MPU  such as  the
MC146805E2
***Versions:...
***Features:...
*OPTi...
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*SIS...
*Symphony...
**SL82C490   'Wagner' 486?              [no datasheet]               ?
***Notes:...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
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