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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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**IBM AT: MC146818 Real Time Clock                                 <84
***Info:
The MC146818  Real-Time Clock  plus RAM is  a peripheral  device which
includes   the   unique   MOTEL   concept   for   use   with   various
microprocessors,  microcomputers,  and  larger computers.   This  part
combines  three unique  features:  a complete  time-of-day clock  with
alarm and one hundred year calender, a programmable periodic interrupt
and square-wave generator,  and 50 bytes of low-power  static RAM. The
MC146818  uses high-speed  CMOS  technology to  interface  with 1  MHz
processor busses, while consuming very little power.

The  Real-Time Clock  plus RAM  has two  distinct uses.  First,  it is
designed  as a  battery powered  CMOS part  (in an  otherwise NMOS/TTL
system) including  all the common battery backed-up  functions such as
RAM, time,  and calendar.  Secondly, the  MC146818 may be  used with a
CMOS  microprocessor  to  relieve  the  software  of  the  timekeeping
workload  and to  extend  the available  RAM  of an  MPU  such as  the
MC146805E2
***Versions:...
***Features:...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C490   'Wagner' 486?              [no datasheet]               ?
***Notes:...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
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