[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88
***Info:...
***Versions:...
***Features:...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91
***Info:...
***Configurations:...
***Features:
o   100% EISA compatible
o   20/25/33/50 MHz 80486 DX/SX CPU operation
o   25/33/40 Mhz 80386DX CPU Operation
o   Integrated write back cache controller with built-in tag comparator
o   Concurrent CPU-cache and EMA/master operations with bus snooping
o   Only ten TTL components are required
o   Complete EISA system can be built on a baby AT sized motherboard
o   Flexible cache size from 64KB to 1MB
o   Page mode DRAM operation supporting 1 to 4 banks up to 256MB
o   Video/system BIOS, shadowing and caching
o   Supports both conventional and concurrent configurations
o   Inclusive secondary cache for snoop filtering
o   Synchronous EISA bus clock
o   Transparent Gate A20 and CPU reset
o   CPU local bus device support
o   Supports 80387, 80487SX and Weitek 3167/4167 co-processors
o   Decoupled refresh without holding CPU
o   Staggered DRAM refresh to minimize power supply noise
o   Rlch set of register options to allow customization
o   Three 160-pin PQFP packages in low power and high speed 0.8um CMOS 
    Technology
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...