[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C360   'Haydn' 80386DX/SX chipset [no datasheet]         c:Jun91
***Notes:
from:
http://www.cbronline.com/news/symphony_introduces_the_haydn_family

"Santa Clara, California-based  Symphony Laboratories Inc has unvieled
a family  of highly integrated core  logic chip sets for  all forms of
AT-alike personal  computers: the Haydn family  comprises the SL82C460
set for  80486 systems and the  SL82C360 set for  80386 machines; each
set includes two devices, a system controller and a bus controller and
an optional cache controller chip  can be added if cache capability is
required;  the   parts  are  in  volume  production   and  a  complete
motherboard can be created with as few as eight active components plus
memory; all operate at 50MHz and  beyond and the sets are supported by
all  major BIOS  vendors; the  sets cost  from $50  to $100  apiece in
quantities of 100-up."

***Configurations:...
**SL82C460   'Haydn II' 80486 chipset   [no datasheet]         c:Jun91...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...