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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**440 series:...
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**?????  (Profusion)    c:99...
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**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance  PC/AT platforms.   This chipset will  support 486SX/
DX/DX2/DX4  and P24T microprocessors  in the  most cost  effective and
power  efficient  designs  available  today.  For  power  users,  this
chipset offers optimum performance for systems running up to 50MHz.

Based  fundamentally  on  OPTi's   proven  82C801  and  82C802  design
architectures,  the 82C895 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The  820895  supports the  latest  write-back  processor designs  from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for   compatibility  and   performance.   It  also   includes  an
82C206-compatible  Integrated Peripherals Controller  (IPC). all  in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.

2.1 Power Management

This block diagram [see  datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN  strategy.  System designs  can easily accommodate
both SLe  and non-SLe  CPUs. If  an Intel non-SLe  CPU is  used, SMI#,
SMIACT#, and  FLUSH# are no  connects.  One design can  easily accomm-
odate both types of processors with minimal changes for upgrades.

***Configurations:...
***Features:...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950        LPC I/O                                         <07/16/99
***Info:...
***Versions:...
***Features:
o   Low Pin Count Interface
    - Comply with Intel LPC Interface Specification Rev. 1.0 
      (Sept. 29, 1997)
    - Supports Serial IRQ Protocol
    - Supports PCI PME# Interface
o   PC98/PC99, ACPI Compliant
    - PC98 & PC99 compliant
    - Register sets compatible with "Plug and Play ISA Specification 
      Rev. 1.0a"
    - ACPI V. 1.0 compliant
    - Supports 9 logical devices
o   Enhanced Hardware Monitor
    - Built-in 8-bit Analog to Digital Converter
    - 3 thermal inputs from remote thermistors or thermal diode or 
      diode-connected transistor
    - 8 voltage monitor inputs (VBAT is measured internally.)
    - WatchDog comparison of all monitored values
o   Fan Speed Controller
    - Provides Fan ON/OFF and PWM control
    - 3 programmable Pulse Width Modulation (PWM) Fan control outputs
    - Each PWM output supports 128 steps of PWM modes
    - Monitors 3 Fan tachometer inputs
o   Game Port
    - Built-in 558 quad timers and buffer chips
    - Supports direct connection of two joysticks
    - Game port signals are multiplexed with GPIOs
o   Two 16C550 UARTs
    - Supports two standard Serial ports
    - UART1 is dedicated for Serial port
    - UART2 supports  either Serial Port or IrDA 1.0/ASKIR
o   Consumer Remote Control (TV remote) IR with Power-up Feature
o   IEEE 1284 Parallel Port
    - Standard mode -- Bi-directional SPP compliant
    - Enhanced mode -- EPP V. 1.7 and 1.9 compliant
    - High speed mode -- ECP, IEEE 1284 compliant
    - Backdrive current reduction
    - Printer power-on damage reduction
    − Supports POST (Power-On Self Test) Data Port
o   Floppy Disk Controller
    - Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy 
      disk drives
    - Enhanced digital data separator
    - 3-Mode drives supported
    - Supports automatic write protection via software
o   48 General Purpose I/O Pins
    - Input mode supports switch de-bounce
    - SMI is routed through GPIOs
o   Flash ROM Interface
    - Up to 4M bits flash supported
o   Single 24/48 MHz Clock Inputs
o   Single +5V Power Supply
o   128-Pin PQFP

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