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**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93
***Notes::...
***Info:...
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the Intel Pentium microprocessor
o Three chip PC/AT solution: 82C596, 82C597 and 82C206
o Supports Intel Pentium CPU address pipelining
o IX clock source, supporting systems running up to 66 MHz
o Adaptive Write Back, direct-mapped cache with size
selections: 64K, 128K, 256K, 512K, 1Mb, 2Mb
o Programmable cache write policy: adaptive write back (AWB),
write-back or write through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycle at 66 MHz
o Built-in TAG auto-invalidation circuitry
o Support for two programmable non-cacheable/system memory "hole"
regions
o Supports two banks of 64-bit wide DRAMs with 256K,
512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs
o Supports DRAM configurations up to 128 Mb
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Provides Flash ROM support
o 33 MHz asynchronous 32-bit VESA VL Local Bus support
o Performance oriented snoop-line comparator for VL/ISA bus masters
o Extended DMA page register
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Low power, high speed CMOS technology
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950 LPC I/O <07/16/99
***Info:
The SIS950 is a LPC Interface based highly integrated Super I/O. The
SIS950 provides the most commonly used legacy Super I/O functionality
plus the latest Environment Control initiatives, such as Hardware
Monitor, Fan Speed Controller and SiS’s "SmartGuardian" function. The
device’s LPC interface complies with Intel "LPC Interface
Specification Rev. 1.0" (Sept. 29, 1997). The SIS950 meets the
"Microsoft PC98 & PC99 System Design Guide" requirements and is ACPI
compliant.
The SIS950 features the enhanced hardware monitor providing 3 thermal
inputs from remote thermistors, thermal diode or diode-connected
transistor (2N3904). The device also provides the SiS innovative
intelligent automatic Fan ON/OFF & speed control functions
(SmartGuardian) to reduce overall system noise and power consumption.
The SIS950 has integrated nine logical devices, featuring an
Environment Controller (controls three Fans). The Environment
Controller has temperature, voltage and Fan Speed monitors. One Fan
Speed Controller is responsible to control three fan speeds through
three 128 steps of Pulse Width Modulation (PWM) output pins and to
monitor three fan's tachometer inputs.
Other features include one high-performance 2.88MB floppy disk
controller, with digital data separator, supporting two 360K/ 720K/
1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance
parallel port features the bi-directional Standard Parallel Port
(SPP), the Enhanced Parallel Port (EPP V. 1.7 and EPP V. 1.9 are
supported), and the IEEE 1284 compliant Extended Capabilities Port
(ECP). Two 16C550 standard compatible enhanced UARTs perform
asynchronous communication, and support IR, one consumer remote
control (TV remote) IR, one MPU-401 UART mode compatible MIDI port,
one game port with built-in 558 quad timers and buffer chips to
support direct connection of 2 joysticks, and six ports (48 GPIO
pins). There is also a flash ROM interface with Address (FA[0:18]),
Data (FD[0:7]), and supporting three control signals FCS#, FWE# and
FRD#. In addition, a SmartGuardian engine is provided to monitor the
system condition and reacts to the detected condition accordingly.
These nine logical devices can be individually enabled or disabled via
software configuration registers. The SIS950 utilizes power-efficient
circuitry to reduce power consumption. Once a logical device is
disabled, the inputs are gated inhibit, the outputs are TRI-STATE and
the input clock is disabled. The SIS950 requires a single 48/24 MHz
clock input and operates with a single +5V power supply.
The SIS950 is available in 128-pin PQFP (Plastic Quad Flat Package).
***Versions:...
***Features:...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
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