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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950        LPC I/O                                         <07/16/99
***Info:...
***Versions:...
***Features:
o   Low Pin Count Interface
    - Comply with Intel LPC Interface Specification Rev. 1.0 
      (Sept. 29, 1997)
    - Supports Serial IRQ Protocol
    - Supports PCI PME# Interface
o   PC98/PC99, ACPI Compliant
    - PC98 & PC99 compliant
    - Register sets compatible with "Plug and Play ISA Specification 
      Rev. 1.0a"
    - ACPI V. 1.0 compliant
    - Supports 9 logical devices
o   Enhanced Hardware Monitor
    - Built-in 8-bit Analog to Digital Converter
    - 3 thermal inputs from remote thermistors or thermal diode or 
      diode-connected transistor
    - 8 voltage monitor inputs (VBAT is measured internally.)
    - WatchDog comparison of all monitored values
o   Fan Speed Controller
    - Provides Fan ON/OFF and PWM control
    - 3 programmable Pulse Width Modulation (PWM) Fan control outputs
    - Each PWM output supports 128 steps of PWM modes
    - Monitors 3 Fan tachometer inputs
o   Game Port
    - Built-in 558 quad timers and buffer chips
    - Supports direct connection of two joysticks
    - Game port signals are multiplexed with GPIOs
o   Two 16C550 UARTs
    - Supports two standard Serial ports
    - UART1 is dedicated for Serial port
    - UART2 supports  either Serial Port or IrDA 1.0/ASKIR
o   Consumer Remote Control (TV remote) IR with Power-up Feature
o   IEEE 1284 Parallel Port
    - Standard mode -- Bi-directional SPP compliant
    - Enhanced mode -- EPP V. 1.7 and 1.9 compliant
    - High speed mode -- ECP, IEEE 1284 compliant
    - Backdrive current reduction
    - Printer power-on damage reduction
    − Supports POST (Power-On Self Test) Data Port
o   Floppy Disk Controller
    - Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy 
      disk drives
    - Enhanced digital data separator
    - 3-Mode drives supported
    - Supports automatic write protection via software
o   48 General Purpose I/O Pins
    - Input mode supports switch de-bounce
    - SMI is routed through GPIOs
o   Flash ROM Interface
    - Up to 4M bits flash supported
o   Single 24/48 MHz Clock Inputs
o   Single +5V Power Supply
o   128-Pin PQFP

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