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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950        LPC I/O                                         <07/16/99
***Info:...
***Versions:...
***Features:
o   Low Pin Count Interface
    - Comply with Intel LPC Interface Specification Rev. 1.0 
      (Sept. 29, 1997)
    - Supports Serial IRQ Protocol
    - Supports PCI PME# Interface
o   PC98/PC99, ACPI Compliant
    - PC98 & PC99 compliant
    - Register sets compatible with "Plug and Play ISA Specification 
      Rev. 1.0a"
    - ACPI V. 1.0 compliant
    - Supports 9 logical devices
o   Enhanced Hardware Monitor
    - Built-in 8-bit Analog to Digital Converter
    - 3 thermal inputs from remote thermistors or thermal diode or 
      diode-connected transistor
    - 8 voltage monitor inputs (VBAT is measured internally.)
    - WatchDog comparison of all monitored values
o   Fan Speed Controller
    - Provides Fan ON/OFF and PWM control
    - 3 programmable Pulse Width Modulation (PWM) Fan control outputs
    - Each PWM output supports 128 steps of PWM modes
    - Monitors 3 Fan tachometer inputs
o   Game Port
    - Built-in 558 quad timers and buffer chips
    - Supports direct connection of two joysticks
    - Game port signals are multiplexed with GPIOs
o   Two 16C550 UARTs
    - Supports two standard Serial ports
    - UART1 is dedicated for Serial port
    - UART2 supports  either Serial Port or IrDA 1.0/ASKIR
o   Consumer Remote Control (TV remote) IR with Power-up Feature
o   IEEE 1284 Parallel Port
    - Standard mode -- Bi-directional SPP compliant
    - Enhanced mode -- EPP V. 1.7 and 1.9 compliant
    - High speed mode -- ECP, IEEE 1284 compliant
    - Backdrive current reduction
    - Printer power-on damage reduction
    − Supports POST (Power-On Self Test) Data Port
o   Floppy Disk Controller
    - Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy 
      disk drives
    - Enhanced digital data separator
    - 3-Mode drives supported
    - Supports automatic write protection via software
o   48 General Purpose I/O Pins
    - Input mode supports switch de-bounce
    - SMI is routed through GPIOs
o   Flash ROM Interface
    - Up to 4M bits flash supported
o   Single 24/48 MHz Clock Inputs
o   Single +5V Power Supply
o   128-Pin PQFP

**Other:...
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