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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950        LPC I/O                                         <07/16/99
***Info:
The SIS950 is  a LPC Interface based highly  integrated Super I/O. The
SIS950 provides the most  commonly used legacy Super I/O functionality
plus  the latest  Environment  Control initiatives,  such as  Hardware
Monitor, Fan Speed Controller  and SiS’s "SmartGuardian" function. The
device’s   LPC   interface   complies   with  Intel   "LPC   Interface
Specification  Rev.  1.0" (Sept.  29,  1997).   The  SIS950 meets  the
"Microsoft PC98 &  PC99 System Design Guide" requirements  and is ACPI
compliant.

The SIS950 features the  enhanced hardware monitor providing 3 thermal
inputs  from  remote  thermistors,  thermal diode  or  diode-connected
transistor  (2N3904).  The device  also  provides  the SiS  innovative
intelligent   automatic   Fan  ON/OFF   &   speed  control   functions
(SmartGuardian) to reduce overall system noise and power consumption.

The  SIS950   has  integrated  nine  logical   devices,  featuring  an
Environment  Controller   (controls  three  Fans).    The  Environment
Controller has  temperature, voltage and  Fan Speed monitors.  One Fan
Speed Controller  is responsible to  control three fan  speeds through
three 128  steps of  Pulse Width Modulation  (PWM) output pins  and to
monitor three fan's tachometer inputs.

Other  features  include   one  high-performance  2.88MB  floppy  disk
controller, with  digital data  separator, supporting two  360K/ 720K/
1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance
parallel  port  features  the  bi-directional Standard  Parallel  Port
(SPP), the  Enhanced Parallel  Port (EPP  V.  1.7 and  EPP V.  1.9 are
supported),  and the  IEEE 1284  compliant Extended  Capabilities Port
(ECP).   Two  16C550  standard   compatible  enhanced   UARTs  perform
asynchronous  communication,  and  support  IR,  one  consumer  remote
control (TV  remote) IR, one  MPU-401 UART mode compatible  MIDI port,
one  game port  with  built-in 558  quad  timers and  buffer chips  to
support  direct connection  of 2  joysticks,  and six  ports (48  GPIO
pins).  There is  also a flash ROM interface  with Address (FA[0:18]),
Data (FD[0:7]),  and supporting three  control signals FCS#,  FWE# and
FRD#. In addition,  a SmartGuardian engine is provided  to monitor the
system condition and reacts to the detected condition accordingly.

These nine logical devices can be individually enabled or disabled via
software configuration registers.  The SIS950 utilizes power-efficient
circuitry  to  reduce power  consumption.  Once  a  logical device  is
disabled, the inputs are gated  inhibit, the outputs are TRI-STATE and
the input  clock is disabled. The  SIS950 requires a  single 48/24 MHz
clock input and operates with a single +5V power supply.

The SIS950 is available in 128-pin PQFP (Plastic Quad Flat Package).

***Versions:...
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