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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**950        LPC I/O                                         <07/16/99
***Info:...
***Versions:...
***Features:
o   Low Pin Count Interface
    - Comply with Intel LPC Interface Specification Rev. 1.0 
      (Sept. 29, 1997)
    - Supports Serial IRQ Protocol
    - Supports PCI PME# Interface
o   PC98/PC99, ACPI Compliant
    - PC98 & PC99 compliant
    - Register sets compatible with "Plug and Play ISA Specification 
      Rev. 1.0a"
    - ACPI V. 1.0 compliant
    - Supports 9 logical devices
o   Enhanced Hardware Monitor
    - Built-in 8-bit Analog to Digital Converter
    - 3 thermal inputs from remote thermistors or thermal diode or 
      diode-connected transistor
    - 8 voltage monitor inputs (VBAT is measured internally.)
    - WatchDog comparison of all monitored values
o   Fan Speed Controller
    - Provides Fan ON/OFF and PWM control
    - 3 programmable Pulse Width Modulation (PWM) Fan control outputs
    - Each PWM output supports 128 steps of PWM modes
    - Monitors 3 Fan tachometer inputs
o   Game Port
    - Built-in 558 quad timers and buffer chips
    - Supports direct connection of two joysticks
    - Game port signals are multiplexed with GPIOs
o   Two 16C550 UARTs
    - Supports two standard Serial ports
    - UART1 is dedicated for Serial port
    - UART2 supports  either Serial Port or IrDA 1.0/ASKIR
o   Consumer Remote Control (TV remote) IR with Power-up Feature
o   IEEE 1284 Parallel Port
    - Standard mode -- Bi-directional SPP compliant
    - Enhanced mode -- EPP V. 1.7 and 1.9 compliant
    - High speed mode -- ECP, IEEE 1284 compliant
    - Backdrive current reduction
    - Printer power-on damage reduction
    − Supports POST (Power-On Self Test) Data Port
o   Floppy Disk Controller
    - Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy 
      disk drives
    - Enhanced digital data separator
    - 3-Mode drives supported
    - Supports automatic write protection via software
o   48 General Purpose I/O Pins
    - Input mode supports switch de-bounce
    - SMI is routed through GPIOs
o   Flash ROM Interface
    - Up to 4M bits flash supported
o   Single 24/48 MHz Clock Inputs
o   Single +5V Power Supply
o   128-Pin PQFP

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