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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Walt States at 66 MHz
    - Two-way Set Associative
    - Write-Back with MESI Protocol
    - Concurrent CPU Bus and Memory Bus Operation
    - Boundary Scan
o   Pentium Processor
    - Chip Set Version of Pentium Processor
    - Superscalar Architecture
    - Enhanced Floating Point
    - On-chip SK Code and SK Data Caches
    - See Pentium Processor User's Manual Volume 2 for more 
      Information
o   Highly Flexible
    - 256K to 512K with parity
    - 32, 64, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous, and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers, and Burst Orders
o   Full Multiprocessing Support 
    - Concurrent CPU, Memory Bus, and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read-for Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
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*SIS...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96
***Info:
The SiS5596/5513  with built-in VGA controller is  a two-chip solution
for Pentium PCI/ISA system. A portion  of on board DRAM is shared with
the  built-in  VGA  controller.  In  that  way,  the  system  cost  is
substantially reduced.

The SiS5596/5513 two chips  solution for shared memory architecture is
achieved by  allowing both  GUI / VGA,  and System DRAM  controller to
control system memory. For  the shared memory application, the chipset
always acts  as the  arbiter of memory  bus masters. Whenever  the GUI
wants to  access the memory bus,  it requests the memory  bus from the
chipset first.  The chipset grants the  memory bus to the GUI, only if
the memory bus is not needed by the chipset. The chipset also supports
the two priority  scheme. Other important key features  such as direct
access frame buffer and memory access latency are also supported.

***Configurations:...
***Features:...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
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