[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96
***Info:...
***Configurations:...
***Features:
o   Supports Intel Pentium CPU and other compatible CPU at 
    66/60/50MHz (external clock speed)
o   Supports VGA Shared Memory Architecture
    - Direct Memory Accesses
    - Shared Memory Area 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M, 4M.
    - Built-in 2-Priority Scheme.
o   Supports the Pipelined Address Mode of Pentium CPU.
o   Integrated Second Level (L2) Cache Controller
    - Write Through and Write Back Cache Modes
    - 8 bits or 7 bits Tag with Direct Mapped Cache Organization
    - Supports Pipelined Burst SRAM.
    - Supports 256 KBytes to 1 MBytes Cache Sizes.
    - Cache Read/Write Cycle of 3-1-1-1 Pipelined Burst SRAM at 66 
      Mhz and 3-1-1-1-1-1-1-1 at back to back read cycle.
o   Integrated DRAM Controller
    - Supports 4 RAS lines, the memory size is from 4MBytes up to 
      512Mbytes.
    - Supports 256K/512K/1M/2M/4M/16M x N 70ns FP/EDO DRAM
    - Supports 4K Refresh DRAM
    - Supports 3V or 5V DRAM.
    - Supports Symmetrical and Asymmetrical DRAM.
    - Supports 32 bits/64 bits mixed mode configuration
    - Supports Concurrent Write Back
    - Table-free DRAM Configuration, Auto-detect DRAM size, Bank 
      Density, Single/Double sided DRAM, EDO/ FP DRAM for each bank
    - Supports CAS before RAS "Intelligent Refresh"
    - Supports Relocation of System Management Memory
    - Programmable CAS# Driving Current
    - Fully Configurable for the Characteristic of Shadow RAM (640 
      KByte to 1 Mbyte)
o   Supports EDO/FP 5/6-2-2-2/-3-3-3 Burst Read Cycles
o   Two Programmable Non-Cacheable Regions
o   Option to Disable Local Memory in Non-Cacheable Regions
o   Shadow RAM in Increments of 16 KBytes
o   Supports SMM Mode of CPU.
o   Supports CPU Stop Clock.
o   Supports Break Switch.
o   Provides High Performance PCI Arbiter.
    - Supports 4 PCI Master.
    - Supports Rotating Priority Mechanism.
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead.
    - Supports Concurrency between CPU to Memory and PCI to PCI.
o   Integrated PCI Bridge
    - Supports Asynchronous PCI Clock.
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Provides CPU-to-PCI Read Assembly and Write Disassembly 
      Mechanism
    - Translates Sequential CPU-to-PCI Memory Write Cycles into PCI 
      Burst Cycles.
    - Zero Wait State Burst Cycles.
    - Supports Advance Snooping for PCI Master Bursting.
    - Maximum PCI Burst Transfer from 256 Bytes to 4 KBytes.
o   388-Pin BGA Package.
o   0.5μm CMOS Technology.

**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...