[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL6012  Memory Mapper for PC-AT (74LS612 compatible)          <Jul87
***Info:
The SL6012 Memory  Mapper is intended for use in  PC-AT design. It can
expand an address bus by 4  bits. In PC-AT applications, 4 bits of the
source  address   are  used  to  select   1  of  16,   eight  bit  map
registers. These registers  are normally programmed (through software)
with the  starting address of each  memory page. The  register data is
output directly for  use as the most significant  bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.

As shown  in Table 1  [see datasheet], the  SL6012 has three  modes of
operation; read, write and map. Data may be written into, or read from
the Memory  Mapper when  chip select CSN  is low. The  register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is  low, data is written  into a register from  the data bus. When
RWN is high  data is output from a Memory Mapper  register to the data
bus.

The map mode of operation is selected when chip select CSN is high. In
this mode, the  register data selected by the  map address inputs (MA0
through  MA3)  will be  available  on  the  map outputs  (MO0  through
MO7).  Note that  the map  registers are  addressed by  either  the RS
inputs or  the MA inputs depending  upon the operating  mode. When MEN
(Map Enable) is low the map  outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.

***Versions:...
***Features:...
**SL9010  System Controller (80286/80386SX/DX, 16/20/25MHz)     <oct88...
**SL9020  Data Controller                                       <oct88...
**SL9025  Address Controller                                    <oct88...
**SL9090  Universal PC/AT Clock Chip                            <oct88...
**SL9250  Page Mode Memory Controller (16/20MHz 8MB Max)        <oct88...
**SL9350  Page Mode Memory Controller (16/20/25MHz 16MB Max)    <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98
***Info:
The SiS5591/5592  SiS5595 glueless P5  A.G.P. chipset provides  a high
performance/cost index  Desktop/Mobile solution for  the Intel Pentium
P54C/P55C, AMD K5/K6, and Cyrix M1/M2 A.G.P. system.

The SiS5591/SiS5592  A.G.P./PCI controller integrated  the Host-to-PCI
bridge, the L2 cache  controller, the DRAM controller, the Accelerated
Graphics  Port interface,  and the  PCI IDE  controller. The  L2 cache
controller can  support up to 1  M P.B. SRAM, and  the DRAM controller
can  support EDO/FP/SDRAM memory  up to  768 MB  with optional  ECC or
parity check  function. The  A.G.P. 1.0 compliance  interface supports
both  1X, and  2X speed  mode with  sideband address  capability.  The
built-in fast  PCI IDE  controller supports the  ATA PIO/DMA,  and the
Ultra DMA/33 functionality.

SiS5591  and SiS5592  have some  pin-out switching  to  facilitate the
main-board layout.  SiS5591 pin  assignment is based  on the  ATX form
factor,  and  SiS5592  pin  assignment   is  based  on  the  NLX  form
factor. Beside  the pin-out switching, SiS5591 and  SiS5592 is totally
the same on the internal logic circuit.

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA,  and  Serial  IRQ  capability,  the ACPI/Legacy  PMU,  the  Data
Acquisition  Interface, the Universal  Serial Bus  host/hub interface,
and the ISA  bus interface which contains the  ISA bus controller, the
DMA controllers,  the interrupt controllers,  and the Timers.  It also
integrates the Keyboard controller, and the Real Time Clock (RTC). The
built-in USB controller,  which is fully compliant to  OHCI (Open Host
Controller  Interface),  provides two  USB  ports  capable of  running
full/low speed USB devices.  The Data Acquisition Interface offers the
ability of monitoring and reporting the environmental condition of the
PC. It could  monitor 4 positive analogue voltage  inputs, 2 Fan speed
inputs, and one temperature input.


***Configurations:...
***Features:...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...