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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT44          Secondary Cache                                c:Jun92
***Info:...
***Versions:...
***Features:
General Features
o   Support for 4868X/DX/DX2 CPUs
o   System implementation with Headland’s HTK340 chip set and future 
    486 chip sets
o   16, 20, 25 and 33 MHz CPU speeds

Memory Configurations
o   32KB, 64KB, 128KB, 256KB, 512KB & 1MB cache sizes
o   25ns SRAMs required at 33 MHz
o   Asynchronous and synchronous SRAMs are supported
o   Programmable write-protected and non-cacheable regions are 
    supported through the chip set

Architecture
o   Look-Aside
o   Write through
o   Direct mapped
o   Integrated tag comparator
o   Zero wait state cache hits
o   Simultaneous 486 and secondary cache update on read miss
o   486 line burst cycle support
Package & Die
o   84-pin PLCC
o   LSI Logic’s 0.7 micron HCMOS process

**Other:...
*HMC (Hulon Microelectronics)...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**5120           Pentium PCI/ISA Chipset (Mobile)            <01/28/97
***Info:
The SiS5120  is a highly  integrated single chip solution  for Pentium
PCI/ISA system. It consists of Host-to-PCI bridge function, PCI to ISA
bridge  function,  PCI IDE  function,  Universal  Serial Bus  host/hub
function.

SiS 5120  supports Enhanced  Power Management, including  legacy Power
Management  Unit  and   Advanced  Configuration  and  Power  Interface
(ACPI).  It also  supports ATA  Synchronous DMA  transfer  protocol to
improve  the IDE performance  and Common  Architecture for  moving ISA
function to PCI to improve system performance.


***Versions:...
***Features:...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset                <04/02/95...
**5511/5512/5513 Pentium PCI/ISA                             <06/14/95...
**5571           (Trinity) Pentium PCI/ISA Chipset (75MHz)   <12/09/96...
**5581/5582      (Jessie)  Pentium PCI/ISA Chipset (75MHz)   <04/15/97...
**5591/5592/5595 (David)   Pentium PCI A.G.P. Chipset        <01/09/98...
**5596/5513      (Genesis) Pentium PCI Chipset               <03/26/96...
**5597/5598      (Jedi)    Pentium PCI/ISA Chipset           <04/15/97...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
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*Unresearched:...
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*Winbond...
*ZyMOS...
*General Sources:...