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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:
Overview
The 82C895 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. This chipset will support 486SX/
DX/DX2/DX4 and P24T microprocessors in the most cost effective and
power efficient designs available today. For power users, this
chipset offers optimum performance for systems running up to 50MHz.
Based fundamentally on OPTi's proven 82C801 and 82C802 design
architectures, the 82C895 adds additional memory configurations and
extensive power management control for the processor and other
motherboard components.
The 820895 supports the latest write-back processor designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus for compatibility and performance. It also includes an
82C206-compatible Integrated Peripherals Controller (IPC). all in a
single 208-pin PQFP (Plastic Quad Flat Pack) package for low cost.
2.1 Power Management
This block diagram [see datasheet] exemplifies the flexibility of the
82C895/82C602 GREEN strategy. System designs can easily accommodate
both SLe and non-SLe CPUs. If an Intel non-SLe CPU is used, SMI#,
SMIACT#, and FLUSH# are no connects. One design can easily accomm-
odate both types of processors with minimal changes for upgrades.
***Configurations:...
***Features:...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**85C471/407 Green PC ISA-VLB 486 Single Chip <94
***Info:
The SiS85C47l, single chip controller supports Intel's 80486DX2/DX/
SX/SL Enhanced, P24D/P24T/P24C CPU, Cyrix's Cx486S2 (M6/M7) CPU and
AMD's Am486DXL/DXLZ CPU.
The Si885C471 is a high performance, 100% PC/AT compatible single chip
controller, designed for cached/non-cached P24D/P24T/P24C, M6/M7 or
486 PC systems. The high integration of the powerful cache controller,
the DRAM controller, the CPU interfaces, the bus controller, the data
buffers and the peripheral controllers provides an easy and economical
solution for compact board manufacturing.
In addition to supporting burst reads for the cache line fills of the
CPU, the SiS85C47l is capable of accepting burst write data of the
CPU's internal cache dirty line(s) during CPU write-back cycles. The
support of the CPU burst write cycle is optional through the control
of the Configuration Registers. The SiS85C471 supports the cache size
up to l MB and the DRAM size up to 128 MB.
The SiS85C471 has a built-in cache controller which supports direct
mapped write-through/write-back cache. The programmable AT-bus clock
supports are compatible with AT-bus timing requirements for different
PC systems.
In addition, the local bus interfaces, the integration of the DMA
Controllers, Interrupt Controllers and Timers/Counters are designed to
be a higher performance, more compact, and more cost-effective product
for a P24D/PZ4T/PZ4C, 486SX/DX/DX2/SL-Enhanced, Am486DXL/DXLZ, or a
Cx48682 (M6/M7) PC/AT system.
The SiS85C47I provides power saving features to allow a system,
through the control of BIOS, to reduce the CPU clock frequency from
50MHz down to 0 MHz(STOP CLOCK) when the system is idle.
To support the SL-Enhanced 486, M6/M7, P24D/P24T/P24C's Am486DXL/DXL2
STPCLK/SMI features, the SiS85C47l also implements the corresponding
logics to support STPCLK /SMI for power saving.
The SiSSSC471 supports the VL-Bus applications including (1) CPU
accesses VL-Bus targets, (2) VL-Bus master mode, and (3) DMA or ISA
master accesses VL-Bus targets.
The SiS85C471 provides flexible ways in configuring the system
depending on whether cache or VESA local bus masters are
supported. The different configurations require different numbers of
external components.
***Configurations:...
***Features:...
**85C496/497 486-VIP 486 Green PC VESA/ISA/PCI Chipset <95...
**85C501/502/503 Pentium/P54C PCI/ISA Chipset <01/09/95...
**5101/5102/5103 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5120 Pentium PCI/ISA Chipset (Mobile) <01/28/97...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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