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**440 series:
***440FX (Natoma)       05/06/96
Chips:         
[82441FX] (PMC) [82442FX] (DBX) [82371SB] (PIIX3)
CPUs:          Single or Dual P-Pro/P-II
DRAM Types:    FPM EDO BEDO
Mem Rows:      8         
DRAM Density:  16Mbit 64Mbit               
Max Mem:       1GB                  
ECC/Parity:    Both  
AGP speed:     not supported
Bus Speed:     50 60 66    
PCI Clock/Bus: 1/2 PCI 2.1              


***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98
Chips:         
[82443BX] (PAC) [82371EB] (PIIX4E)
CPUs:          Single or Dual P-II/P-III/Celeron
DRAM Types:    EDO SDRAM Reg SDRAM ESDRAM
Mem Rows:      6 EDO, 8 SDRAM, 8 Reg SDRAM, 8 ESDRAM
DRAM Density:  16Mbit 64Mbit 128Mbit*1
Max Mem:       1GB
ECC/Parity:    Both
AGP speed:     1x 2x
Bus Speed:     66 100 133*2
PCI Clock/Bus: 1/2 1/3 1/4*2 PCI 2.1


>*1 Only in C-1 and later steppings.

>*2 Exists  but unofficially. There is  no 1/2 divider  for AGP, 
    making AGP unstable in a 133MHz bus system. In this config. the 
    system is overclocked.

***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C895         System/Power Management Controller (cached)   c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D 
    - AMD 486DX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct Mapped Cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page-hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
    - Programmable wait states for DRAM reads and writes
    - Enhanced DRAM configuration map
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
    - Programmable wake-up events through hardware, software and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
    - One programmable GREEN event timer
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
    - Integrates DMA, timer and interrupt controllers
    - Optional PS/2 style IRQ1 and 12 latching
o   VESA VL interface:
    - Conforms to the VESA v2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high-speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Unresearched:...
*VIA...
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*Winbond...
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