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**800 series
***810         (Whitney)       04/26/99...
***810L        (Whitney)       04/26/99...
***810-DC100   (Whitney)       04/26/99...
***810e        (Whitney)       09/27/99...
***810e2       (Whitney)       01/03/01...
***815         (Solano)        06/19/00...
***815e        (Solano-2)      06/19/00...
***815em       (Solano-?)      10/23/00...
***815ep       (Solano-3)      c:Nov'00...
***815p        (Solano-3)      c:Mar'01...
***815g        (Solano-3)      c:Sep'01...
***815eg       (Solano-3)      c:Sep'01...
***820         (Camino)        11/15/99...
***820e        (Camino-2)      06/05/00...
***830M        (Almador)       07/30/01...
***830MP       (Almador)       07/30/01...
***830MG       (Almador)       07/30/01...
***840         (Carmel)        10/25/99...
***845         (Brookdale)     09/10/01...
***845MP       (Brookdale-M)   03/04/02...
***845MZ       (Brookdale-M)   03/04/02...
***845E        (Brookdale-E)   05/20/02...
***845G        (Brookdale-G)   05/20/02...
***845GL       (Brookdale-GL)  05/20/02...
***845GE       (Brookdale-GE)  10/07/02...
***845PE       (Brookdale-PE)  10/07/02...
***845GV       (Brookdale-GV)  10/07/02...
***848P        (Breeds Hill)   c:Aug'03...
***850         (Tehama)        11/20/00...
***850E        (Tehama-E)      05/06/02...
***852GM       (Montara-GM)    01/14/03...
***852GMV      (Montara-GM)    ???...
***852PM       (Montara-GM)    06/11/03...
***852GME      (Montara-GM)    06/11/03...
***854         (?)             04/11/05
Chips:
[82854](GMCH) [82801DBM] (ICH4-M) 	
CPUs:          Celeron M ULV
DRAM Types:    DDR 266/333
Mem Rows:      --
DRAM Density:  ?
Max Mem:       2GB
ECC/Parity:    no
AGP speed:     no, Integrated Extreme Graphics 2
Bus Speed:     400 MT/s (100 MHz QDR)
PCI Clock/Bus: 1/3  PCI 2.2


***855GM       (Montara-GM)    03/12/03...
***855GME      (Montara-GM)    03/12/03...
***855PM       (Odem)          03/12/03...
***860         (Colusa)        05/21/01...
***865G        (Springdale)    05/21/03...
***865PE       (Springdale-PE) 05/21/03...
***865P        (Springdale-P)  05/21/03...
***865GV       (Springdale-GV) c:Sep'03...
***875P        (Canterwood)    04/14/03...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:...
***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:
The  82C802G/GP  provides  a  highly  integrated  solution  for  fully
compatible,  high  performance  PC/AT  platforms.  This  chipset  will
support  486SX/DX/DX2/DX4 and  P24T microprocessors  in the  most cost
effective  and power  efficient  designs available  today.  For  power
users this  chipset offers optimum performance for  systems running up
to 50MHz.

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C802G/GP  adds additional  memory configurations
and  extensive power management  control for  the processor  and other
motherboard components.

The  82C802G/GP supports  the latest  in write-back  processor designs
from Intel, AMD, and Cyrix, as  well as supporting the AT bus and VESA
local  bus for  compatibility and  performance.  It  also  includes an
82C206  Integrated  Peripherals  Controller  (IPC), all  in  a  single
208-pin PQFP (Plastic Quad Plat Pack) package for low cost.

Power Management Block
Figure  2-1  [see  datasheet]   exemplifies  the  flexibility  of  the
82C802G/GP/82C602   GREEN   strategy.   System  designs   can   easily
accommodate  both SLe and  non-SLe CPUs.  If an  Intel non-SLe  CPU is
used. SMI#, SMIACT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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