[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C802G/GP     System/Power Management Controller (cached)      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
[features found only in the 802GP are marked in [] brackets ]

o   Processor interface:
    - Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
    - AMD 486SX, DX2, DXL, DXL2, Plus
    - Cyrix DX, DX2, M7
    - CPU frequencies supported 20, 25, 33, 40 and 50MHz
o   Cache interface:
    - Direct mapped cache
    - Two banks interleaved or single bank non-interleaved
    - 64, 128, 256 and 512K cache sizes
    - Programmable wait states for L2 cache reads and writes
    - 2-1-1-1 read burst and zero wait state write @ 33MHz
    - No Valid bit required
   [- Supports external single-chip cache modules from thyroid-party ]
   [  vendors for high performance at 50MHz                          ]
    - Supports CPUs with L1 write-back support
o   DRAM interface:
    - Up to 128MB main memory support
    - Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM 
      modules
    - Read page hit timing of 3-2-2-2 at 33MHz
    - Supports hidden, slow. and CAS-before-RAS refresh
    - Four RAS lines to support four banks of DRAM
   [- Eight RAS lines to support four banks of DRAM  ]
    - Programmable wait states for DRAM reads and writes
   [- Programmable memory holes for supporting ISA memory ]
    - Enhanced DRAM configuration map
   [- Strong drivers on the MA lines (12/24mA) ]
   [- Supports asymmetric DRAMs                ]
o   Power management:
    - Support for SMM (System Management Mode) for system power 
      management implementations
    - Programmable power management
   [- CPU clock control ]
    - Programmable wake-up events through hardware, software, and 
      external SMI source
    - Multiple level GREEN support (NESTED_GREEN)
    - STPCLK# protocol support
   [- Programmable GREEN event timer       ](802G  only)
   [- Individually programmable peripheral ](802GP only)
o   ISA interface:
    - 100% IBM PC/AT ISA compatible
   [- Programmable edge- or level-trigger interrupts ]
    - integrates DMA, timer and interrupt controllers
   [- Slew rate control for output drivers           ]
    - Optional PS/2 style IRQ1 and IRQ12 latching
o   VESA VL interface:
    - Conforms to the VESA V2.0 specification
    - Optional support for up to two VL masters
o   Miscellaneous features:                              (802G only)
    - Full support for shadow RAM, write protection, L1/L2 
      cacheability for video, adapter, and system BIOS
    - Enhanced arbitration scheme
    - Transparent 8042 emulation for fast CPU reset and GATEA20 
      generation
o  [Miscellaneous features:                             ](802GP only)
   [- Full support for flash, write protection, L1/L2   ]
   [  cacheability for video, adapter, and system BIOS  ]
   [- Provides Micro Channel bridge support             ]
   [- 10-/16-nit I/O decodes                            ]
   [- Enhanced arbitration scheme                       ]
o   Packaging:
    - Higher integration
    - Reduced TTL count
    - Low-power, high~speed 0.8-micron CMOS technology
    - 208-pin PQFP (Plastic Quad Flat Pack)

**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...