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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:
The  OPTi design  team  is  proud to  present  the  64-bit Pentium  AT
solution with  VESA Local bus. As  always, the product emphasis  is on
value. The OPTi  PTMAWB is crafted to provide  the highest performance
but most cost effective  system solution without compromising quality,
compatibility or reliability.

The  PTMAWB is a  top-of-the-line solution  for the  server/power user
market. Flexibility of design without using the most expensive support
parts has  been given  key importance. This  ensures the  total system
cost to be  at the high-end 486 level - yet  with the high-end Pentium
performance.

The PTMAWB has  the state-of-the-art AWB cache controller  for up to 2
MB  of Adaptive  Write-back cache  support. The  DRAM  controller also
supports posted writes for faster performance on write cycles.

The  OPTi  PTMAWB-V  provides  PC  servers  and  PC  power  users  the
horsepower of the 64-bit Pentium at 60 MHz and 66 MHz-immediately.


***Configurations:...
***Features:...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93
***Notes:...
***info:
The OPTi EISA Pentium chipset consists of two 208-pin QFP devices: the
SYSC, the BUSC and 2 100-pin DBC buffer chips.

The SYSC  write back-memory cache  controller - 82C693 -  controls the
memory  subsystem for EISA  bus controller  accesses between  the CPU,
EISA/ISA masters and DMA devices.  The memory subsystem consists of up
to 8 banks of DRAM with hidden  refresh and from 128K to 1 MB of write
back cache  translates bus control  signals and addresses  between the
CPU, EISA, ISA and DMA masters and slaves.

The BUSC  - 82C696 - integrates  the motherboard I/O  logic defined by
the EISA specification: two  8254 timers, EISA NMI/time-out logic, two
EISA 8259 interrupt controllers, a  32-bit DMA controller and the EISA
system arbiter.

The  Data  Bus Controller  -  82C697  -  integrates data  buffers  and
provides  control for  synchronous data  pipelining. It  also provides
control for bus conversion, Parity generation and checking and an EISA
ID register.  The high  levels of integration and performance provided
by these 4 devices enable OEMs  to plan the evolution of their Pentium
PC/ATs  to  EISA/PCs.   This   chipset  enables  OEMs  to  move  ahead
aggressively  with  high  performance   EISA  platforms  in  order  to
participate successfully in the migration of 32-bit PCs to EISA.

***Configurations:...
***Features:...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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