[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96
***Notes:...
***Info:
The OPTi Viper-N+ chipset is the leading solution for PCI-based mobile
applications.   Viper-N+  features   leading  edge   power  management
capability and  flexibility for Intel Pentium  75/90/100/120 and Cyrix
6x86 processor based  notebooks. The chipset incorporates desktop-like
performance features  such as L1 and  L2 cache support,  a full 64-bit
DRAM  controller  and  an  integrated  PCI  controller,  in  a  highly
integrated three chip set.

In  terms of  advanced  power  management, no  chipset  offers a  more
effective, comprehensive or flexible feature set, allowing for maximum
performance  with  minimum  power  consumption  for  extended  battery
life. In  fact, for typical applications,  Viper-N+'s power management
unit reduces power consumption by as much as 80%.

Viper-N+ offers the highest level  of system integration, enabling the
lowest  system  cost  and  real  estate  requirement  for  Pentium-PCI
notebooks.  A system without TTL is achievable with synchronous cache.
And, PCI  offers easy  upgradability to emerging  standard interfaces,
such  as  PCMCIA/CardBus  and  PCI  docking  stations.  Viper-N+  also
features an integrated local bus IDE  controller to avoid ISA data bus
bottlenecks.

OPTi coupled  its expertise in mobile technology  and PCI-based design
to create its second generation  64-bit CPU mobile chipset. The result
is  Viper-N+,  enabling  the  highest levels  of  performance,  system
integration  and  power management  capability  available for  Pentium
PCI-based mobile systems.

***Configurations:...
***Features:...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93
***Notes:...
***info:
The OPTi EISA Pentium chipset consists of two 208-pin QFP devices: the
SYSC, the BUSC and 2 100-pin DBC buffer chips.

The SYSC  write back-memory cache  controller - 82C693 -  controls the
memory  subsystem for EISA  bus controller  accesses between  the CPU,
EISA/ISA masters and DMA devices.  The memory subsystem consists of up
to 8 banks of DRAM with hidden  refresh and from 128K to 1 MB of write
back cache  translates bus control  signals and addresses  between the
CPU, EISA, ISA and DMA masters and slaves.

The BUSC  - 82C696 - integrates  the motherboard I/O  logic defined by
the EISA specification: two  8254 timers, EISA NMI/time-out logic, two
EISA 8259 interrupt controllers, a  32-bit DMA controller and the EISA
system arbiter.

The  Data  Bus Controller  -  82C697  -  integrates data  buffers  and
provides  control for  synchronous data  pipelining. It  also provides
control for bus conversion, Parity generation and checking and an EISA
ID register.  The high  levels of integration and performance provided
by these 4 devices enable OEMs  to plan the evolution of their Pentium
PC/ATs  to  EISA/PCs.   This   chipset  enables  OEMs  to  move  ahead
aggressively  with  high  performance   EISA  platforms  in  order  to
participate successfully in the migration of 32-bit PCs to EISA.

***Configurations:...
***Features:...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...