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**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
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*OPTi...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:
The  OPTi design  team  is  proud to  present  the  64-bit Pentium  AT
solution with  VESA Local bus. As  always, the product emphasis  is on
value. The OPTi  PTMAWB is crafted to provide  the highest performance
but most cost effective  system solution without compromising quality,
compatibility or reliability.

The  PTMAWB is a  top-of-the-line solution  for the  server/power user
market. Flexibility of design without using the most expensive support
parts has  been given  key importance. This  ensures the  total system
cost to be  at the high-end 486 level - yet  with the high-end Pentium
performance.

The PTMAWB has  the state-of-the-art AWB cache controller  for up to 2
MB  of Adaptive  Write-back cache  support. The  DRAM  controller also
supports posted writes for faster performance on write cycles.

The  OPTi  PTMAWB-V  provides  PC  servers  and  PC  power  users  the
horsepower of the 64-bit Pentium at 60 MHz and 66 MHz-immediately.


***Configurations:...
***Features:
o   100% PC/AT compatible 
o   Fully supports the Intel Pentium microprocessor 
o   Three chip PC/AT solution: 82C596, 82C597 and 82C206 
o   Supports Intel Pentium CPU address pipelining 
o   IX clock source, supporting systems running up to 66 MHz 
o   Adaptive Write Back, direct-mapped cache with size 
    selections: 64K, 128K, 256K, 512K, 1Mb, 2Mb 
o   Programmable cache write policy: adaptive write back (AWB), 
    write-back or write through 
o   Fully programmable cache and DRAM read/write cycles 
o   Supports 3-2-2-2 cache burst read cycle at 66 MHz 
o   Built-in TAG auto-invalidation circuitry 
o   Support for two programmable non-cacheable/system memory "hole" 
    regions 
o   Supports two banks of 64-bit wide DRAMs with 256K, 
    512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs 
o   Supports DRAM configurations up to 128 Mb 
o   Supports 3-3-3-3 pipeline DRAM burst cycles 
o   DRAM post write buffer 
o   Provides Flash ROM support 
o   33 MHz asynchronous 32-bit VESA VL Local Bus support 
o   Performance oriented snoop-line comparator for VL/ISA bus masters 
o   Extended DMA page register 
o   Asynchronous CPU and VL bus interface 
o   AT bus clock speed programmability 
o   Low power, high speed CMOS technology 

**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
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