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*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?
***Info:
Overview
The OPTi Viper-MAX Chipset provides a highly integrated solution for
fully compatible, high performance PC/AT platforms based on the Intel
3.3V Pentium Processor, Cyrix 6x86 Processor, and AMD K86 Proc-
essor. As the latest member of the Desktop Viper Chipset Family, it is
designed from its inception to be the highest performance Pentium
chipset ever. its feature set can be scaled to address entry level
UMA-based system to high-end non-UMA work stations and servers. The
deep buffers in the Viper-MAX minimize system level latencies and
maximize through-puts to both DRAM and PCI subsystems.
The chipset provides 64-bit core logic, with Unified Memory Archit-
ecture (UMA), and integrated PCI support, plus sophisticated power
management features. This highly integrated approach supplies the
foundation for a cost effective platform without compromising per-
formance. Its feature set furnishes an array of control and status
monitoring options that are accessed through a simple and straight-
forward interface. All major BIOS vendors provide extensive software
hooks that allow system designers to integrate their own special
features with minimal effort.
82C566 Data Buffer Controller
The 82C566 performs the task of buffering the CPU to the DRAM memory
data path.
o CPU to memory data buffer
o CPU to PCI local bus buffer
o Memory to PCI local bus buffer
o 208-pin PQFP
82C567 System Controller
The 82C567 provides the control functions for the host CPU interface,
the 64-bit Level-2 (L2) cache, the 64-bit DRAM bus, and the PCI
interface. The 82C567 controls the data flow between the CPU bus, the
DRAM bus, the local buses, and the 8/16-bit ISA bus. It interprets and
translates cycles from the CPU, PCI bus master, ISA master, and DMA to
the host memory, PCI bus slave, or ISA bus devices. The 82C567 also
serves as the UMA (Unified Memory Architecture) and USB (Universal
Serial Bus) protocol interface.
o 3.3V CPU interface
o DRAM controller
o L1/L2 cache controller
o UMA arbiter
o USB interface
o PCI interface
o Arbitration logic
o Data bus buffer control (memory data bus to and from host data
bus)
o 208-pin PQFP
82C568 Integrated Peripherals Controller
The 820568 contains the ISA bus controller and includes an 82C206, RTC
interface, DMA controller, serial interrupt controller and distributed
DMA. It also has a sophisticated system power management unit.
o ISA bus controller
o Master mode IDE
o Type F DMA support
o Integrated 82C206 IPC
o System power management functions
o PCI local bus interface
o PCI to ISA expansion bridge
o Serial interrupt controller
o Distributed DMA
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 092h Register
o 208-pin POFP
***Configurations:...
***Features:
CPU Interface
o Fully supports all Intel 3.3V Pentium processors (P54C, P55C,
P55CT) at 50, 60, and 66.667MHz
o Supports AMD K86 and Cyrix 6x86 processors
o Supports the Cyrix 6x86 processor linear burst mode
o Chipset solution:
- One Data Buffer Controller (82C566)
- One System Controller (82C567)
- One Integrated Peripherals Controller (82C568)
o Supports CPU address pipelining
Cache Interface
o Support four types of devices:
- Synchronous SRAM bursting at 3-1-1-1
- Pipelined burst SRAM bursting at 3-1-1-1
- Sony SONIC-2WP module bursting at 2-1-1-1
- Asynchronous SRAM bursting at 3-2-2-2
o Supports four cache sizes:
- 256KB, 512KB, 1MB and 2MB
o Programmable write policy:
- Write-back
- Adaptive write-back
- Write-through
DRAM Interface
o Supports both Unified Memory Architecture (UMA) and non-UMA
interfaces
o Supports symmetrical and asymmetrical DRAMS
o Supports both 3.3V and 5.0V DRAM devices
o Supports 64-bit wide DRAM devices with 256KB, 512KB, 1MB, 2MB,
4MB, 8MB, and 16MB addressing
o Supports DRAM configurations up to 512MB
o Six banks of FP mode DRAMs (7-3-3-3 at 66MHz)
o Six banks of EDO DRAM support with auto detection (5-2-2-2 at
66MHz)
o Four banks of BEDO (burst EDO) (X-1-1-1 at 66MHz)
o Four banks of SDRAM (synchronous DRAM) (X-1-1-1 at 66MHz)
o Deep buffering for DRAM performance
- Six quad-word CPU-to-DRAM write posting
- 24 double-word PCI-to-DRAM write posting
- 24 double-word DRAM-to-PCI read prefetch
o Supports mixed DRAM memory technologies
- FP mode/EDO/SDRAM
- FP mode/EDO/BEDO
o Memory parity support
o Programmable drive currents for the DRAM control signals
o Hidden refresh with CAS-before-RAS refresh supported
o Self-refresh supported during Suspend mode
o Support for two programmable non-cacheable memory regions
Unified Memory Interface
o Industry Standard UMA implementation
o Compatible with all major graphics chip vendors
o Supports 0.5, 1.0, 2.0, 3.0, and 4.0MB of shared frame, buffer for
GUI (Graphical User interface) within system DRAM
o Two-pin arbitration scheme with multiple request levels
PCI Interface
o PCI Specification 2.1 compliant
- Supports delayed transactions
o X-1-1-1 PCI to memory burst transfer performance (transfer
rate > 100MB/sec)
o Interfaces the CPU and standard buses to Peripheral Component
Interconnect (PCI) operating in synchronous/asynchronous modes
o CPU-to-PCI deep write posting buffers (six double-words)
o PCI-to-DRAM deep write posting and read prefetch buffers
(24 double-words)
o Supports five PCI masters and six ISA slots
o Supports PCI pre-snoop for PCI masters
o PCI byte/word merge support for CPU accesses to PCI bus, and
support for PCI prefetch
o Several levels of concurrence
- PCI-to-PCI / CPU-to-memory
- PCI-to-DRAM / CPU-to-cache
- CPU-to-PCI / GUI-to-memory
IDE Interface
o Integrated bus master IDE conforms to SFF Specification
o Two channels supported (up to four devices)
o PIO Mode transfer support (up to Mode 5)
o Enhanced ATA Specification support
o Single- and/or Multi-Word DMA Mode 2 timing
o Scatter/Gather feature
o Built-in FIFOs with data prefetch and post write support
Universal Serial Bus
o Support for Universal Serial Bus (USB) interface for serial
peripherals
System I/O and Power Management
o Enhanced DMA interface
- Type F DMA for faster device transfer
- Distributed DMA for moving ISA function to PCI
- Buffered DMA for efficient POI/DRAM bandwidth
- Two steerable DMA channels for motherboard plug and play
o Enhanced interrupt interface
- Serial interrupt for moving ISA function to PCI
- Two steerable interrupts for motherboard plug and play
o Includes a fully integrated 820206 with external real-time clock
(RTC) interface
o Facility to read current CMOS index
o "True" GREEN power management support, with support for STPCLK#
modulation and the CPU stop clock state
o Packaged in three 208-pin PQFPs (Plastic Quad Flat Packs)
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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