[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547     Python PTM3V                                     c:94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   100% PC/AT compatible
o   Fully supports the 3.3V/5.0V Pentium processors
o   Three chip solution:
    - 82C547 System Controller (SYSC) (160-pin PQFP)
    - 82C546 AT Bus Controller (ATC) (208-pin PQFP)
    - 82C206 Integrated Peripheral Controller (IPC) (84-pin PLLC 
      or 100-pin PQFP)
o   Two buffer/translator support chips:
    - 82C606A (100-pin PQFP)
    - 82C606B (100-pin PQFP)
o   Supports Pentium CPU address pipelining
o   1X clock source, supporting systems running Pentium processor 
    bus clocks up to 60MHz
o   Write-back, direct-mapped cache with size selections:
    64KB, 128KB, 256KB, 512KB, 1MB and 2MB
o   Programmable cache write policy: write-back or write-through
o   Fully programmable cache and DRAM read/write cycles
o   Supports 3-2-2-2 cache burst read cycles at 60MHz
o   Built-in tag auto-invalidation circuitry
o   Support for two programmable non-cacheable memory regions
o   Options for cacheable, write-protected, system and video BIOS
o   Supports two banks of 64-bit wide DRAMs with 256KB, 512KB, 1MB
    2MB, 4MB and 8MBx36 Page Mode
o   Supports DRAM configurations up to 128MB
o   Supports 3-3-3-3 pipeline DRAM burst cycles
o   DRAM post write buffer
o   Support for flash ROM
o   Shadow RAM option
o   Hidden refresh with CAS-before-RAS refresh supported
o   High-performance 32-bit local bus support
o   Performance-oriented snoop-line comparator for VL/ISA
    bus masters
o   External DMA page register
o   Turbo/slow speed selection
o   Asynchronous CPU and VL bus interface
o   AT bus clock speed programmability
o   Transparent 8042 emulation for Fast CPU Reset and GATEA20 
    generation
o   Supports Ports 92h, Gate A20, and Fast Reset
o   Mixed voltage (3.3V and 5.0V), low-power, high speed, 0.8
    micron CMOS technology

**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...