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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*Headland/G2...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91
***Info:
The HT21  is an  advanced PC/AT compatible,  single-chip 80386SX/80286
design solution.   This highly  integrated single chip  allows simple,
low cost  system design options while featuring  high performance, low
power  consumption,  and minimum  board  space requirements.  Advanced
memory management features  include support for page mode,  2 or 4-way
interleaving in  both pipelined and  non-pipelined modes. The  LIM 4.0
hardware implementation  features dual sets of 32  registers with full
context support for highest performance Optimization of extended local
memory  accesses. An  advanced  EMS hardware  write-protect option  is
provided. The HT21 supports 256K and 1M DRAMs in l by 1, 1 by 4, and 1
by 9 device configurations for up  to 8MB of on-board system memory. A
flexible Shadow  RAM option for  System and Video  BIOS as well  as 8-
16-bit BIOS Options adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT21 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC  core logic requirements. The chip  also contains all
the  necessary  address buffers,  data  transceivers, memory  drivers,
parity  checking   and  supporting  circuitry  for   a  complete  high
performance computer solution. An asynchronous AT Bus clock allows for
a constant 8MHz Bus clock rate for highest bus device compatibility as
defined in  IEEE Spec P996.   In controlled bus applications  the HT21
supports up to a  12 MHz Bus Clock rate. This device  is packaged in a
208-pin Plastic Quad Flat Pack combining several external buffers into
this space saving solution.

***Configurations:...
***Features:...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
**IBM AT: MC146818 Real Time Clock                                 <84
***Info:...
***Versions:...
***Features:
o   Low-Power, High-Speed, High-Density CMOS
o   Internal Time Base and Oscillator
o   Counts Seconds, Minutes, and Hours of the Day
o   Counts Days of the Week, Date, Month, and Year
o   3 V to 6 V Operation
o   Time Base Input Options: 4.194304 MHz, 1.048576 MHz, or 32,768 kHz
o   Time Base Oscillator for Parallel Resonant Crystals
o   40 to 200 uW Typical Operating Power at Low Frequency Time Base
o   4.0 to 20 mW Typical Operating Power at High Frequency Time Base
o   Binary or BCD Representation of Time, Calendar, and Alarm
o   12- or 24-Hour Clock with AM and PM in 12-Hour Mode
o   Daylight Savings Time Option
o   Automatic End of Month Recognition
o   Automatic Leap Year Compensation
o   Microprocessor Bus Compatible [this means absolutely nothing]
o   MOTEL Circuit for Bus Univerality
o   Multiplexed Bus for Pin Efficiency
o   Interfaced with Software as 64 RAM Locations
o   14 Bytes of Clock and Control Registers
o   50 Bytes of General Purpose RAM
o   Status Bit Indicates Data Integrity
o   Bus Compatible Interrupt Signals (IRQ)
o   Three Interrupts are Separately Software Maskable and Testable
      Time-of-Day Alarm, Once-per-Second to Once-per-Day
      Periodic Rates from 30.5 us to 500 ms
      End-of-Clock Update Cycle
o   Programmable Square-Wave Output Signal
o   Clock Output May Be Used as Microprocessor Clock Input
      At Time Base Frequency /1 or /4
o   24-Pin Dual-In-Line Package



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