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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90
***Info:
The  HT12, an IBM  PC/AT compatible  chip, supports  the 80286  CPU at
clock speeds  to 16MHz.  This  highly integrated chip  solution offers
high  performance  and  reliability,  with  low  cost,  minimal  power
consumption,  and low  board-space requirements.  It differs  from the
HT11 by the addition of 4 EMS Registers and an EMS Software Driver.

A  fully PC/AT  compatible system  is  implemented with  this chip  by
adding a CPU/NPU, KBD CNTRL, RTC,  BIOS, Memory and a few low cost TTL
devices.

This  chip supports  64K, 256K  and 1M,  x1 and  x4, DRAMs  in config-
urations up  to 4 Meg.   A 12.5MHz 0  wait-state system can  be imple-
mented using  80ns DRAMs  while a 10MHz  0 wait-state  system requires
100ns  DRAMs.  The  memory  controller also  supports  the shadow  RAM
feature and the  Split Memory option.  The Split  Memory option allows
the System RAM located between 640K and 1M to be remapped above top of
memory.

The HT12 contains CPU  and peripheral support functions; including DMA
controllers, a  memory mapper, timer/counters,  interrupt controllers,
and a bus controller.  This  chip replaces board address buffers, data
transceivers,  memory  drivers, parity  generators  and their  support
circuits. This chip is packaged in a 160 pin Flat Pack.

***Configurations:...
***Features:...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:

The HTK340  chip set is  a two chip, high  performance, cost-effective
solution for the  80486SX DX, and DX2 processing  environments. In its
minimum configuration,  this highly integrated chip  set requires only
four external  TTL devices to  implement a fully compatible  IBM PC/AT
system at speeds up to 33MHZ.

The  HTK340  is based  upon  Headland's  HTK320  Bus Architecture  and
consists of the HT321-ISA  Bus Controller and the HT342-Memory Control
Unit  (MCU). Both  chips are  packaged in  184 pin  plastic  quad flat
packs.

The  HTK340 is unique  in that  it provides  performance approximating
that  of   large  secondary  cache  systems,   including  the  highest
performance  write  back  cache  architectures, without  any  external
cache. Secondary cache solutions  should be considered in applications
that make use of multi-tasking  and large model operating systems. The
Headland  HT44 secondary  cache  was  designed to  meet  the cost  and
performance objectives for these  applications.  The key to this level
of performance is  the 4-level deep write buffer,  which includes byte
gathering for up to 32-bit DRAM writes.

Due to  the effectiveness of the  primary cache internal  to the 80486
most of the bus activity in a PC/AT compatible environment consists of
writes.  Indeed, this  write activity  consists almost  exclusively of
writes of either  bytes or Words (16 bit  entities). In addition, much
of this write  activity is into sequential memory  locations. The byte
gathering feature of the buffer  has the effect of reducing the number
of memory accesses required. Since the 80486 can always write into the
buffer with  zero wait states (assuming  the buffer is  not full), and
the  buffer can  empty faster  than it  can be  filled for  most write
activity, the net effect is that the writes from the CPU never cause a
wait state.

The HTK340 can  support Peripheral Devices such as VGA  or SCSI on the
local processor  bus, or any other  devices that are  designed to work
within  the 80486  bus protocol  and  timing. By  eliminating the  ISA
backplane  bottleneck,  system   designers  can  greatly  improve  the
performance of functions such as graphics generation and disk access.

The  HTK340  supports up  to  4 banks  of  DRAM,  configurable as  1-4
banks. This  flexible memory architecture allows for  any memory type,
from 256K to 16M devices,  in any bank.  Maximum system performance is
achieved  from  the  DRAM   banks  through  various  means,  including
interleaving  of  memory  banks  and/or  paging, and  CAS  before  RAS
refresh. The memory can also be tuned to maximum potential through the
use  of  extensive  DRAM  timing control  registers.   These  controls
include: precharge time, access time  on reads, active time on writes,
as well  as CAS and RAS  delays.  In addition,  further system perfor-
mance is  gained by separate timing  parameters on the  read and write
cycles which allow  system designers to take maximum  advantage of the
pipelined structure of the chip set.

The  HTK340 also  supports  extensive mapping  registers, which  allow
system designers to take maximum  advantage of system memory. The chip
set  supports Shadow/Remap  in  16K  blocks between  the  640K and  1M
boundaries, and eliminates the requirement for external decoding logic
by supporting  26 programmable  non-cache regions. Devices  which meet
HTK340  local bus  requirements  may be  implemented without  external
TTL. The mapping  structure of the HTK340 provides  for a single 8-bit
EPROM to be used for both  the System and Video BIOS, further reducing
system chip count and cost.

***Configurations:...
***Features:...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
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