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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX) 
[82452NX] (RCG) [82451NX] (MIOC) 
[82371EB] (PIIX4E),                            
CPUs:          Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types:    FPM EDO 2-way Interleave 4-way Interleave
Mem Rows:      8
DRAM Density:  16Mbit 64Mbit
Max Mem:       8GB
ECC/Parity:    Both
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3


**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Support for 486SX/DX/DX2 CPU
o   2 - 184 pin PQFP devices
o   Local bus interface
o   16, 20, 25 and 33MHz CPU speeds
o   Fully static operation
o   Weitek 4167 supported
o   System and Video BIOS on single ROM
o   Uses 0.7 Micron HCMOS process
ISA Controller
o   AT Compatible
o   Synchronized 8MHz ISA bus
o   Posted backplane memory writes
o   10 or 16 bit l/O mapping
o   Integrated 82375, 82593 and 8254 functionality
o   Fast gate A20/Fast reset
Write Buffer
o   4 deep on-chip buffer
o   Byte gathering
o   Out of order operation
o   Full or partial write buffer hits
DRAM Controller
o   Line burst capability from DRAM to 80486
o   256K/1M/4M/16M DRAMs
o   Mixed memory types
o   EMS 4.0
o   Hidden refresh operation
o   256MB Maximum system memory
o   Staggered refresh
o   Shadowing in 16KB increments between 640KB and 1MB
o   Remapping
o   Fast paging
o   2 or 4 way interleaving

**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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