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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92
***Notes:...
***Info:...
***Configurations:...
***Features:
o   Support for 486SX/DX/DX2 CPU
o   2 - 184 pin PQFP devices
o   Local bus interface
o   16, 20, 25 and 33MHz CPU speeds
o   Fully static operation
o   Weitek 4167 supported
o   System and Video BIOS on single ROM
o   Uses 0.7 Micron HCMOS process
ISA Controller
o   AT Compatible
o   Synchronized 8MHz ISA bus
o   Posted backplane memory writes
o   10 or 16 bit l/O mapping
o   Integrated 82375, 82593 and 8254 functionality
o   Fast gate A20/Fast reset
Write Buffer
o   4 deep on-chip buffer
o   Byte gathering
o   Out of order operation
o   Full or partial write buffer hits
DRAM Controller
o   Line burst capability from DRAM to 80486
o   256K/1M/4M/16M DRAMs
o   Mixed memory types
o   EMS 4.0
o   Hidden refresh operation
o   256MB Maximum system memory
o   Staggered refresh
o   Shadowing in 16KB increments between 640KB and 1MB
o   Remapping
o   Fast paging
o   2 or 4 way interleaving

**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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