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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HTK320        386DX Chip Set                                 c:Sep91
***Info:...
***Configurations:...
***Features:
o   2-chip 80386DX PC/AT compatible solution
o   Supports CPU speeds of up to 40MHz
o   3167 Weitek and 80387 co-processor supported
o   Peripherals supported on local CPU bus
o   Port 92 functions
o   Posted backplane memory cycles
Cache
o   Direct mapped or 2-way set associative cache sizes of 32K, 
    64K and 128K
o   Internal tag RAMs
o   Zero wait-state write hits
o   Line burst capability from DRAM to cache
WriteBuffer
o   4 deep, 32-bit wide write buffers
o   Byte gathering
o   Full or partial write buffer hit Support
o   Out of order operation
Memory
o   4-bank DRAM Support
o   256K, 1M, 4M, 16M support (up to 256Mb)
o   Mix and match memory types
o   2/4-way or disabled interleaving and fast paging
o   CAS before RAS, or RAS Only Refresh
o   EMS 4.0 support
o   Single BIOS-ROM support 
o   System and Video BIOS in Single ROM

**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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